JPS5932815B2 - data processing system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing system that manually inputs data from the outside into a memory connected to a processor.

FIG. 1 relates to a conventional data processing system.

2. Description of the Related Art A direct memory access (DMA) method is a conventional method for allowing a processor to take in data supplied from a data output device at high speed. FIG. 1 is a conceptual diagram of an information processing device using the DMA method. Normally, in the DMA method, multiple pieces of data are handled as one block. The device REQ on the data sending side issues a transfer request TXRQ to the direct memory access controller (hereinafter referred to as controller) DMAC. The controller DMAC issues a DMA request DR to the processor P. When processor P receives this request DR, it stops the processing that was being executed up to that point and issues a DMA permission signal DG.
The permission signal DG is input to the controller DMAC and at the same time passes through the inverter IN to the gates AGO and DGO.
is closed, and address bus A and data bus D are connected to processor P.
Prevent it from being used by Controller DMAC
When it receives the enable signal DG, it sends a signal to open the gate AGl to this gate AGl, and also sends the memory ME to the address bus A via this opened gate AGl.
Outputs the address for accessing M.

The output address is a predetermined address and is a memory address for writing data from the data output device REQ into the memory MEM. Further, when the controller DMAC receives the permission signal DG, the data output device R
Transfer permission T>(STB is issued for EQ. Signal TXS
The data output device REQ receiving TB sends a signal to open the gate DGl, and outputs the data to the data bus D via the gate DGl. This allows this data to be written to the address location of the memory MEM that has already been output from the controller DMAC. That is, normally, when transferring data from the outside through buses A and D used by processor P, bus A is used by controller DMAC and bus D is used by data output device REQ to write data into memory MEM. Also, as mentioned above, data is sent by block, so
When one piece of data is written to the memory MEM, the address output by the controller DMAC is usually automatically incremented (or subtracted) by 1. When the transfer for one block is completed, the data output device REQ or the controller D
The MAC issues a transfer end signal (not shown in the figure), and the processor P knows that the transfer has occurred, and changes from the stopped state to the running state. In this way, in the DMA system, data within one block can be inputted into the memory MEM at high speed.

However, in order to input the data of the next block into the memory MEM, the processing of the data of the previous block must be completed by the processor P. Therefore, there is a problem in that the speed at which data is transferred from the data output device REQ to the memory MEM is limited by the data processing speed by the processor P. The present invention solves these conventional problems, and even when the processor is processing the previous data,
An object of the present invention is to provide a data transfer device that can write data into a memory from the outside.

FIG. 2 is a block diagram of the embodiment.

In Figure 2, the same symbols as in Figure 1 refer to the same items as in Figure 1. The memory MEM has an address A as shown in FIG.

From A. The area up to is a data transfer area for storing data from the data output device REQ. This area should be large enough to store data for multiple programs. When transferring data, the data output device REQ outputs a transfer request TXRQ as in the conventional case.

The controller DMAC sends a DMA request DR to the processor P, as in the conventional case, and in response to this request, the processor P stops processing and sends a permission signal DG.

Controller DMAC sends transfer permission signal TXSTB to data output device REQ in response to this permission signal DG. At this time, the gates AGO and DGO are activated by the signal DG.
is considered off. In response to this transfer permission signal TXSTB, the data output device REQ outputs the number of words SC to be transferred.
is sent as data to the memory MEM via the data line D.

The controller DMAC transfers this data to the memory MEM
Start address A within the transfer area. A built-in address counter (not shown) causes address A to be stored on address line A. Output. Data output device R
The EQ then sends the data word by word to the data line D, and the controller DMAC updates the address output from the address counter one by one and sends it to the address line A. In this way, data of the number of words equal to the number of words SC is stored in the memory MEM. After transferring these data, the data output device REQ increments the counter CN by 1 via the count up line UP. The output of the counter CN is input to an OR circuit 0R, and this OR circuit 0R issues an interrupt request to the processor P via an interrupt line 1NT when the contents of the counter CN are other than zero. When processor P receives an interrupt, it reads memory address A. Take out the number of words SC from , know the number of transferred words, and move to address A. Extract data with the number of words equal to the number of transferred words SC from the next area,
Process. At this time, the processor P has the number of words SC and the start address A. From this, calculate the address a1 to which the data of the next block will be transferred, store this, and when the next block is transferred, address A1. Instead, prepare to retrieve data from address A. Furthermore, after processing the data, the processor P causes the counter CN to count down using the countdown line DN. Data output device R
After the above-mentioned data transmission, when the EQ wants to further transmit one block's worth of data, it outputs the number of words to be transferred and the data to be transferred to the data line D in exactly the same manner as described above.

At this time, the controller DMAC uses a counter in the controller DMAC to sequentially set addresses for data storage of one block from address a1 in the memory MEM to the address line A1.
Send to. Therefore, even if the processor P has not yet processed the data stored at the location starting from the address in the memory MEM, the next data can be stored in the memory MEM without rewriting this data.
In response to the interrupt signal from the interrupt signal line 1NT, the processor P sequentially reads data from this address a1 of the memory MEM.As mentioned above, the processor P calculates this address from the previously read data. I remember that. Thereafter, the data output device REQ can similarly sequentially send data of a plurality of blocks to the memory MEM.

At this time, the processor P counts down the counter CN after processing data for one block in the memory MEM. Therefore, the counter CN indicates the number of blocks of unprocessed data currently in the memory MEM. Memory ME
Since the capacity of the M transfer area is finite, if data is stored sequentially in this manner, a situation may arise in which data exceeding the capacity of the prepared transfer area must be stored.

To prevent this, the controller DMAC uses address A.
. After storing up to address A again. Provide a function to store data from. For this purpose, after the address counter counts the address AO, the address is output cyclically so as to set AO. This function is usually called a data chain, and is a commercially available controller DM.
It is already installed in AC. In this case, the data output device REQ inputs data to the area up to the address An, and then inputs the data to the area up to the address An.

To input data into the area from address A.
Data starting from must already be processed by processor P. Otherwise, data transfer from the data output device REQ must be prohibited.
Therefore, the output of the counter CN is decoded by the decoder DEC and notified to the data output device REQ via the transfer mask line MSK. That is, when the contents of the counter CN reach a certain value, the data output device REQ prohibits data transfer. Maximum number of words transferred in one block and memory M
This constant value is determined from the capacity of the EM transfer area.

For example, if the maximum number of words in one block is 100, the memory ME
If the capacity of the transfer area of M is 500, the decoder DEC
Therefore, it is sufficient to configure the circuit so that the 1111 signal is output when the value of the counter CN reaches 5. In this way, even if the processor P has not finished processing the data that has already been transferred, the data output device REQ can transfer the next data.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional data processing system, FIG. 2 is a diagram showing an embodiment of the present invention, and FIG. 3 is an explanatory diagram of a data transfer area of a memory used in the present invention. P...Processor, DMAC...Direct memory access controller, REQ...
・Data output device, MEM...Memory.

Claims (1)

[Claims] 1. A data processing device, a memory, a data output device,
a control circuit for storing data from the data output device in the memory; a counter for counting the amount of data transferred to the memory for each block; and the contents of the counter satisfy a first condition. In some cases, the processing apparatus includes means for outputting a data processing request to the processing apparatus, and means for prohibiting data transfer of the data output apparatus when the content of the counter satisfies a second condition. , means for causing the counter to count in a first direction after processing of data accessed in the memory in response to the data processing request, and the data output device outputting data to the memory block by block. and means for counting the counter in a direction opposite to the first direction after transferring the data. 2. The data output device outputs transfer amount data representing the amount of data to be transferred to the memory together with the data to be transferred, and after reading the transfer amount data from the memory, the processing device , the data processing system according to claim 1, wherein the data amount indicated by the transfer amount data is read from the memory. 3. The data processing system according to item 2, wherein the control circuit cyclically outputs an address indicating a data consolidation position within the data transfer area. 4. Clause 2, wherein the data processing device has a function of determining a starting address of data to be read next from the transfer amount data of the previously processed data and the store address of the data in the memory. or the data processing system described in Section 3.