JPS5933258B2 - Mold for semiconductor devices - Google Patents
Mold for semiconductor devicesInfo
- Publication number
- JPS5933258B2 JPS5933258B2 JP6338677A JP6338677A JPS5933258B2 JP S5933258 B2 JPS5933258 B2 JP S5933258B2 JP 6338677 A JP6338677 A JP 6338677A JP 6338677 A JP6338677 A JP 6338677A JP S5933258 B2 JPS5933258 B2 JP S5933258B2
- Authority
- JP
- Japan
- Prior art keywords
- mold
- lead frame
- protrusion
- semiconductor device
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Moulds For Moulding Plastics Or The Like (AREA)
- Injection Moulding Of Plastics Or The Like (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
【発明の詳細な説明】
この発明は半導体素子のモールド用金型にかゝり、特に
コイニング加工の施された台床を備えたリードフレーム
のモールドに適する半導体素子のモールド用金型に関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a mold for molding a semiconductor device, and more particularly to a mold for molding a semiconductor device that is suitable for molding a lead frame having a coined base.
一例の半導体素子のリードフレームに第１図に断面側面
図を示する如く、リードフレーム１の一部に半導体素子
配設用の台床１ａを有するとともに、この台床における
半導体素子配設部にコイニング加工を施して１主面に設
けられた凹部ｌｂと、反対主面に生じた突起Ｉｃとを有
するものがある。As shown in the cross-sectional side view of FIG. 1, an example of a lead frame for a semiconductor element has a base 1a for arranging a semiconductor element in a part of the lead frame 1, and a part of the base for arranging a semiconductor element. Some have a recess lb formed on one main surface by coining and a protrusion Ic formed on the opposite main surface.
この突起の高さををにて表わす。かゝるリードフレーム
は第２図に断面図示する如き一対の上下金型２ａ、２ｂ
の対接面間に形成されたキャビティ２ｃ、２ｃ’内に嵌
入され、キャビティ内にエポキシの如き合成樹脂３を圧
入加熱して施される。上記台床における半導体素子の配
設面と反対主面（図における下面）は半導体装置の動作
による発熱を良好に放散させるため、モールドを施さず
露出される。これには前記キャビティに台床の前記反対
主面（図の下面）を密接させることによつてモールド樹
脂の回りこみを阻止しようとしている。しかし、実際に
モールドが施された半導体装置についてみると多少のバ
ラツキはあるもモールド樹脂のフラッシュが認められる
。フラッシュは軽度のものは除去することはできるが、
機械的に擦過除去するため製品の外観を損する欠点があ
る。さらに重度の場合は除去することが不能で放熱に害
があるのみならず、外観上からも製品にならないという
重大な欠点がある。この発明は半導体素子の従来のモー
ルド用金型の欠点を改良する構造のモールド用金型を提
供するものである。The height of this protrusion is expressed by . Such a lead frame consists of a pair of upper and lower molds 2a and 2b as shown in cross section in FIG.
The synthetic resin 3, such as epoxy, is fitted into the cavities 2c and 2c' formed between the opposing surfaces, and is applied by press-fitting and heating a synthetic resin 3 such as epoxy into the cavities. The main surface of the pedestal opposite to the surface on which the semiconductor element is disposed (the lower surface in the figure) is exposed without being molded in order to properly dissipate heat generated by the operation of the semiconductor device. This is done by bringing the opposite main surface (lower surface in the figure) of the base into close contact with the cavity to prevent the mold resin from going around. However, when looking at semiconductor devices that have actually been molded, flash of the molding resin is observed, although there is some variation. Mild flashes can be removed, but
Since it is mechanically removed by abrasion, it has the disadvantage of damaging the appearance of the product. Furthermore, in severe cases, it is impossible to remove, which not only harms heat dissipation, but also has the serious drawback that it cannot be used as a product due to its appearance. The present invention provides a molding die having a structure that improves the drawbacks of conventional molding dies for semiconductor devices.
この発明の半導体素子のモールド用金型は、上下金型の
それぞれ相対向する面に設けられたリードフレーム嵌入
用のキャビティに、リードフレームのコイニングの施さ
れた台床の突起を内封する座ぐりを設けたことを特徴と
する。The semiconductor device molding die of the present invention has a seat for enclosing the protrusion of the coined base of the lead frame in a cavity for inserting the lead frame provided on the opposing surfaces of the upper and lower molds. It is characterized by having a hole.
次に本発明を一実施例の半導体素子のモールド用金型に
つき図面を参照して詳細に説明する。第３図に示す本発
明の一実施例のモールド用金型は、上下金型１２ａ、１
２ｂの夫々相対向する面に設けられたリードフレーム１
を嵌入するためのキャビティ１２ｃ、１２ｃ’に、リー
ドフレームにおけるコイニングＩｂの施された台床Ｉｂ
の突起Ｉｃを内封する座ぐり１２ｄ、１２ｄ’が設けら
れる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail with reference to the drawings regarding an embodiment of a mold for a semiconductor device. The molding die according to one embodiment of the present invention shown in FIG.
Lead frames 1 provided on opposing surfaces of 2b.
In the cavities 12c and 12c' for inserting the coining Ib in the lead frame, the platform Ib
Counterbore 12d and 12d' are provided to enclose the projection Ic.
前記座ぐりは台床の突起の高さをよりも大なるか等しい
深ざを！’）（ι′≧を）なる如くする。The depth of the counterbore is greater than or equal to the height of the protrusion on the base! ') (ι′≧).
またその径は突起の径よりも大なるか等しくし、突起を
光分に内封する如くする。この発明によればキヤビテイ
にモールド樹脂３を圧入したとき下型の金型１２ｂの底
面は座ぐり部以外の部分で密接するため、モールド樹脂
が台床の下面（半導体装置における露出面）に回りこみ
不所望に附着することが皆無となつた。Further, its diameter is set to be larger than or equal to the diameter of the protrusion so that the protrusion is enclosed in the light. According to this invention, when the mold resin 3 is press-fitted into the cavity, the bottom surface of the lower mold 12b comes into close contact with the portion other than the counterbore, so that the mold resin spreads around the bottom surface of the base (the exposed surface of the semiconductor device). There are no more unwanted incidents.
これにより従来の構造のモールド金型にあつては第２図
に示される如く、コイニングの突起１ｃがキヤビテイの
底面に衝接し、台床の平面（下面における）部との間に
間隙ｖを生じ、これにモールド樹脂が回りこむことによ
りフラツシユを生ずるものと解明された。上述の如くし
て半導体装置における台床が放熱板としての機能を充分
達成するとともに、デイフラツシングの要もなくなり工
程が短縮され、さらに半導体装置の外観も向上されると
いう顕著な利点がある。また本発明は突起が至つて容易
である上に金型の損耗も減少するという利点もある。As a result, in the case of a mold having a conventional structure, the protrusion 1c of the coining collides with the bottom surface of the cavity, creating a gap v between it and the flat (lower surface) part of the base, as shown in FIG. It was revealed that flashing occurs when the mold resin wraps around this. As described above, there are significant advantages in that the base of the semiconductor device fully functions as a heat sink, there is no need for day flushing, the process is shortened, and the appearance of the semiconductor device is improved. Further, the present invention has the advantage that protrusion is extremely easy and wear and tear on the mold is reduced.
第１図は半導体素子の断面側面図、第２図は従来のモー
ルド用金型にリードフレームを装入した状態を示す断面
図、第３図はこの発明の一実施例のモールド用金型にリ
ードフレームを装入した状態を示す断面図である。
なお図中同一符号は同一または相当部分を夫々示すもの
とする。１・・・・・・リードフレーム、１ａ・・・・
・・リードフレームの台床、１ｂ・・・・・・コイニン
グ、１ｃ・・・・・・コイニングの突起、１２ａ，１２
ｂ・・・・・・上下の金型、１２ｃ，１２ｃ′・・・・
・・金型のキヤビテイ、１２ｄ，１２ｄ・・・・・・キ
ヤビテイの座ぐり。FIG. 1 is a cross-sectional side view of a semiconductor element, FIG. 2 is a cross-sectional view showing a state in which a lead frame is inserted into a conventional molding die, and FIG. 3 is a cross-sectional view of a molding die according to an embodiment of the present invention. FIG. 3 is a sectional view showing a state in which a lead frame is inserted. Note that the same reference numerals in the drawings indicate the same or corresponding parts, respectively. 1...Lead frame, 1a...
... Lead frame base, 1b... Coining, 1c... Coining protrusion, 12a, 12
b... Upper and lower molds, 12c, 12c'...
...Mold cavity, 12d, 12d...Spot face of cavity.
Claims (1)
加工凹部、反対主面に前記コイニング加工により突起を
生じた台床を含むリードフレームにモールド封止を施す
ためのモールド用金型にして、上下金型のそれぞれ相対
向する面に設けられたリードフレーム嵌入用のキャビテ
ィに前記突起を内封する座ぐりを具備したことを特徴と
する半導体素子のモールド用金型。1. A molding die for mold-sealing a lead frame including a coining concave portion on the main surface where semiconductor pellets are to be disposed, and a platform having a protrusion formed by the coining process on the opposite main surface, A mold for molding a semiconductor device, characterized in that a cavity for inserting a lead frame provided on opposing surfaces of the upper and lower molds is provided with a counterbore for enclosing the protrusion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6338677A JPS5933258B2 (en) | 1977-06-01 | 1977-06-01 | Mold for semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6338677A JPS5933258B2 (en) | 1977-06-01 | 1977-06-01 | Mold for semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS53149765A JPS53149765A (en) | 1978-12-27 |
| JPS5933258B2 true JPS5933258B2 (en) | 1984-08-14 |
Family
ID=13227797
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6338677A Expired JPS5933258B2 (en) | 1977-06-01 | 1977-06-01 | Mold for semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5933258B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5460565A (en) * | 1977-10-21 | 1979-05-16 | Nec Home Electronics Ltd | Parts molding method |
-
1977
- 1977-06-01 JP JP6338677A patent/JPS5933258B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS53149765A (en) | 1978-12-27 |
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