JPS5934069B2 - Converter gate control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides two
A gate control method for a converter formed by connecting two unit converters in antiparallel, in which two single pulses having a phase difference of 600 degrees are combined as gate pulses supplied to individual thyristors of each unit converter. The gate of the converter uses a double pulse, and when switching the direction of the load current, after one unit converter has no current, the other unit converter is activated and the load current rises in the new direction. Regarding control method.

This type of converter is used as a static Leonard device that performs four-quadrant operation of a DC motor, or as a cycloconverter that performs four-quadrant operation of an AC motor.
FIG. 1a shows the gate pulse generation circuit of this type of converter, and FIG. 1b shows the main circuit.

Two unit converters CONI make up the converter main circuit
, CON2 each consist of three-phase bridge-connected thyristors U1 to Z or U2 to Z2. Both unit converters conduct currents in opposite directions to a load (not shown). Here, the unit converter CONI will be called a forward side converter, and the unit converter CON2 will be called a reverse side converter. Gate pulse generator G belonging to each converter CONI, CON2
NI and GN2 each receive a synchronizing signal SYNC taken out from a three-phase AC power supply to which both converters are commonly connected via an instrument transformer (not shown), and the firing angle is determined based on the synchronizing signal. A gate pulse can be given to the corresponding thyristor at a firing angle according to the command signal V. In this case, the pulse generator G belonging to the forward converter
The firing angle command signal V is directly guided to N1Vr-, whereas the firing angle command signal V is guided to the pulse generator GN2 belonging to the opposite converter via a polarity inversion circuit. Signal P
, N are switching signals given from a switching command calculator (not shown). Therefore, the pulse generator GNI,G
N2 receives firing angle command signals that are inversely related to each other, so that when one is operating in a firing angle range that outputs a forward conversion voltage, the other outputs a corresponding reverse conversion voltage. Able to operate in angular range. However, in the end, the switching signals P and N are used to cause only one of them to output a gate pulse. For example, in the process of switching the positive load current flowing through the forward converter GNl to the negative direction, after the positive load current flowing through the forward converter GNl becomes zero! the switching signal P is inverted to prevent the pulse generator GNl from generating an output;
Thereafter, the switching signal N is inverted and the inhibition of output generation of the pulse generator GN2 is released. However, even if the block of the pulse generator is released, the gate pulse is not necessarily immediately supplied to the thyristor pair in the corresponding unit converter that should be turned on at that time.

This is because, as is well known, double pulses consisting of two narrow single pulses each having a phase difference of 60 degrees are used as the gate pulses U1 to Zl and U2 to Z2 of each thyristor in this type of converter. Because there is. The first single pulse forming a double pulse occurs at the regular firing timing of the relevant thyristor, whereas the subsequent single pulse should fire at a 60 sequence delay phase than the relevant thyristor. It is ignited. By supplying gate pulses to the two thyristors at the same time in this way, the current can be started from the start even when the load current is not continuous. However, when the blocking of the pulse generator is released, the regular firing timing of any of the thyristors as described above does not necessarily arrive immediately, but may arrive with a maximum delay of 600 degrees. Since there is a switching dead time of up to 60 cycles, especially in applications such as cycloconverters where switching between converters is performed every half cycle of the output frequency, the switching dead time is reduced as the output frequency increases. The problem arises that the load current is significantly distorted from the desired waveform. To avoid this problem, a wide pulse with a width of 60 or more, for example 1200, may be used as the gate pulse, and the pulse generator supplies the gate pulse to the thyristor pair to be turned on immediately after the block is released. can be started.

However, when using such wide pulses, the pulse transformer required to insulate and supply gate pulses to each thyristor becomes large, and the ignition power supply also requires a large capacity. It has disadvantages such as being large due to its size. SUMMARY OF THE INVENTION An object of the present invention is to prevent the occurrence of the above-mentioned switching dead time while employing the commonly used double-pulse method in order to avoid the above-mentioned drawbacks.

According to the present invention, in the converter gate control method as described at the beginning, in order to cause the load current to rise in a new direction, immediately after an operation command is given to the unit converter corresponding to that direction. , is achieved by generating an additional gate pulse which forces the thyristor pair in the unit converter to be turned on at that time to fire without waiting for the occurrence of the regular gate pulse.

FIG. 2 shows the main parts of a circuit device for implementing the gate control method according to the present invention.

In this figure, 1 is a logic circuit attached to the pulse generator GN1 for the forward converter CON1, and 2 is a logic circuit attached to the pulse generator GN1 for the forward converter CON2. U guided to each of logic circuits 1 and 2
, ~Z, , U2 ~ Z2 are all the well-known double pulses described above. Although the internal configuration of only logic circuit 1 is shown here, logic circuit 2 also has exactly the same internal configuration. The double pulses U1-Z1 corresponding to the individual thyristors U1-Z, of the forward converter CONl are respectively led to AND gates G1-G6. These AND gates G1 to G6 commonly receive a switching signal P as the other input.
be guided. During operation of the forward converter CONl, the switching signal P is ! 1111 (at this time, the switching signal N input to the logic circuit 2 is in the 11011 state).
) Therefore, each of the double pulses U1 to Z1 is outputted through an AND gate each time, and is supplied as a gate pulse to the corresponding thyristor U1 to Z1 via a pulse amplification section and a pulse transformer (not shown). . The switching signal is 110! ! When the signal is reversed, the AND gates G1 to G6 enter a blocking state, and the passage of the double pulse is blocked. The portions described so far correspond to the conventional circuit. However, in such a conventional system, when the switching signal P inverts from 11011 to 11111 coincidentally coincides with the generation timing of any of the double pulses U1 to Z, only K immediately fires the appropriate thyristor pair. I can't do it.

In the worst case, i.e. any pulse U1-Z
Immediately after the generation timing of 1 has passed, the switching signal becomes 1101.
From 1! When switching to 1111, the gate pulse will not be supplied unless the pulse generation timing after 601 is reached, and the rise of the load current will be delayed. When attempting to supply a current with a sinusoidal waveform, for example, to a load by means of a cycloconverter, a delay in the rise of the current due to switching dead time becomes a problem, and the waveform distortion becomes unacceptably large, especially at high output frequencies. Therefore, according to the present invention, flip-flops FF1 to FF6 are first provided, each double pulse U1 to Z1 is led to the set input terminal of the flip-flops FF1 to FF6, respectively, and 60 pulses are input to the set input terminal of the flip-flops FF1 to FF6. The corresponding pulses are directed to the thyristors to be fired with a delay.

As a result, flip-flops FFl to FF6 are sequentially set to 6
While outputting a 00-width output signal, the last arriving single pulse is memorized each time. Furthermore, the outputs of the flip-flops FFl to FF6 are connected to other AND gates Gl3 to Gl.
8, and the other input ends of these AND gates Gl3 to Gl8 are coupled to the output end of a monostable multivibrator MSl to which a switching signal is input. The outputs of these AND gates Gl3 to Gl8 are outputted to the OR gates G7 to Gl together with the outputs of the AND gates G1 to G6 described above.
It is guided by 2. Furthermore, and gates Gl3 to Gl
The outputs of 8 are also input to the OR gates corresponding to the 60-ad lead thyristors. By taking such measures according to the present invention, the switching signal P changes from 1!0!1 to 1111! Even if it is reversed, the flip-flop FF
Memory of l~FF6 [Therefore, AND gate Gl3~G
Since the appropriate one of I8 is open, the output pulse of the monostable multivibrator passes through that one AND gate, and an additional gate pulse is supplied to the appropriate thyristor pair in an interrupt manner by the OR combination of G7 to Gl2. be done.

For example, the switching signal P is generated immediately after the regular firing timing of the thyristor Z1 has passed, that is, immediately after the first single pulse of the double pulse Z1 is generated! 011 to Illll
・Assume that it is reversed.

The thyristor pair that should be brought into conduction immediately after this is Zl and Ul. According to the circuit according to the present invention, in this case, only the flip-flop FF2 is placed in the set state by the first single pulse of the double pulse Z, which occurs immediately before the inversion of the switching signal. Only AND gate GL4 is open. Therefore, the output pulse of the monostable multivibrator, which operates as soon as the switching signal is reversed, is equal to its open AND gate Gl.
4 and is transmitted as gate pulses to two thyristors Zl and Ul via OR gates G8 and G7.
According to the present invention, immediately after an operation command is given to a unit converter corresponding to a new direction in order to cause the load current to rise in that direction, conduction is established at that time in the unit converter. By generating an additional gate pulse that forcibly fires the thyristor pair without waiting for the generation of the regular gate pulse, even though the double pulse method is adopted, the point caused by the regular gate pulse can be avoided. It is possible to start ignition without waiting for the arrival of the arc timing, to minimize dead time in control, and to make the load current follow the current target value well.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a cycloconverter for explaining a conventional gate control method, and FIG. 2 is a main circuit diagram for explaining a gate control method according to the present invention. CONl, CON2...unit converter, GNl, GN2
...gate pulse generation circuit, 1,2...logic circuit,
G1-D6, Gl3-Gl8...and gate, G7
~Gl2...OR gate, FFl~FF2...flipflop.

Claims (1)

[Claims] 1 A gate control method for a converter in which two unit converters each consisting of a three-phase thyristor bridge are connected in antiparallel, and the gate pulses supplied to the individual thyristors of each unit converter are at a position of 60° from each other. A double pulse that is a combination of two single pulses with a phase difference is used, and when switching the direction of the load current, after one unit converter has no current, the other unit converter is activated to change the load current in the new direction. In a converter gate control method that causes load current to start up in a new direction, immediately after an operation command is given to a unit converter corresponding to that direction in order to start up a load current, By generating an additional gate pulse that forcibly fires a thyristor pair that should sometimes conduct without waiting for the regular gate pulse to occur, the wasted time in the process of switching the direction of the load current is shortened. A converter gate control method characterized by: