JPS5935525B2 - variable delay circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a variable delay circuit, and an object of the present invention is to always maintain a flat frequency characteristic up to a frequency band required by a signal to be delayed.

Variable delay circuits are used in various circuits whose purpose is to change the time axis.

One example is a video phase stabilizer used to correct the time axis of a reproduced signal in a VTR.

In a VTR, time axis errors such as jitter and skew occur during reproduction of recorded signals.

This time axis error can be reduced by applying servo control to the mechanical system, but it cannot be completely corrected.

The video phase stabilizer corrects this remaining time axis error, detects the time axis error using an external reference synchronization signal, and changes the delay time of the delay circuit through which the playback signal passes according to the error. Correction is made by

The variable delay circuit has various configurations, but an inductive M type circuit using an electrically controllable variable capacitance diode is often used.

FIG. 1 shows the configuration of an inductive M-type variable delay circuit.

The structural unit of this delay circuit is a variable capacitance diode 103
A block 101 consisting of a coil 102 having inductive coupling with
It is constructed as a unit.

By connecting these blocks in series, the required delay time can be obtained.

The signal to be delayed that enters from terminal 1A and the control signal line 1
Since the capacitance of the variable capacitance diode 103 changes according to the potential difference between the control signal 06 and the control signal 06, the delay time τ of the delay line changes.
=KOv/King C1■ Frequency band t=1. 〒 and (L: capacitance of coil, C: capacitance of variable capacitance diode, Ko, K, : proportionality constant)
changes.

Therefore, by changing the potential of the control signal, the delay time can be varied.

If the control signal has an alternating current component, this one block causes the control signal to be superimposed on the signal to be delayed through the variable capacitance diode.

Therefore, in the next block 104, the control signal line 105
As the control signal for the delay, a signal having a polarity opposite to that of the control signal on the control signal line 106 with respect to the signal to be delayed is used.

With this configuration, the control signals cancel each other out and are prevented from being superimposed on the signal to be delayed.

However, the inductive M-type variable delay circuit as described above,
By changing the capacitance of the variable capacitance diode (hereinafter referred to as C) according to the control signal, the frequency band of the delay line, f
o""K1-JTN changes and the frequency band becomes minimum where C becomes maximum due to the control signal.

(This value is fgπ) Now, when the frequency band f1 required by the signal to be delayed is wide, the number of delay line stages required per stage is t to obtain the required amount of change in delay time. Since the delay time becomes small, the number becomes very large.

(For example, when f 1 = 20 MHz and the amount of change in delay time is 100 ns, the number of stages required is 60 or more,
In the case of 200 ns, the number of stages is 170 or more.

(As a variable capacitance diode, the capacitance change range is 17pF.
~4 pF).

Therefore, in order to minimize the number of stages of the delay line to obtain the necessary amount of change in delay time, the minimum frequency of the delay line must be set near the frequency band f1 required by the signal to be delayed.

At this time, the frequency characteristics drop around f1 due to the fact that the band of the delay line is only up to fl, and the capacitance C of the variable capacitance diode of the delay line reaches its maximum, resulting in mismatching.

Therefore, it is necessary to compensate for the frequency characteristics around f1.

For example, if this compensation is performed using a common emitter amplifier circuit and a capacitor is used for high frequency compensation, the frequency characteristic f of the delay line.

If fo is near f groove π, it will compensate correctly, but even if fo is sufficiently larger than f groove I, it will compensate for the high range with the same characteristics above f11, resulting in overcompensation, and the frequency characteristics will not be flat, which is inconvenient. It is.

Figure 2 shows this state, where A is f.

-fl, Dldf. 〉f, indicates the time.

Further, A shows the frequency characteristic of the delay line, B shows the high frequency compensation characteristic of the common emitter amplification circuit, and C shows the frequency characteristic of the variable delay circuit that performs high frequency compensation on the output of the delay line.

The above problem can be solved as follows.

That is, the band f of the delay line. f depending on. By increasing the amount of high-frequency compensation when fo is around f1, and decreasing the amount of high-frequency compensation when fo>fl, it is possible to always keep the frequency characteristics flat until fl.

In the present invention, a variable capacitance diode is used as a capacitor for high frequency compensation, and a control signal to be applied to the delay line is applied to this variable capacitance diode to change the amount of high frequency compensation according to the frequency band of the delay line, thereby adjusting the frequency characteristics. It is an attempt to level things out.

This variable capacitance diode may be the same as or different from that of the delay line.

) An embodiment of the present invention is shown in FIG.

The input signal from the terminal 4A is sent to the impedance conversion circuit 4.
01 (In this example, it is composed of an emitter follower.

) and a matching resistor before entering the variable delay line 402.

Furthermore, the control signal generation circuit 403 generates a control signal and applies it to the variable capacitance diode of the variable delay line 402.

This control signal changes the capacitance of the variable capacitance diode, and changes the delay time and frequency band.

The delayed signal passes through an impedance conversion circuit 404 composed of an emitter follower circuit, and then enters a common emitter amplification circuit 405.

This common emitter amplifier circuit 405 includes variable capacitance diodes 409 and 410 for high frequency compensation on the emitter side.
are connected in parallel so that their polarities are opposite to each other and through a capacitor 407 for cutting DC components.

From the resistor 4081, variable capacitance diodes 409, 41
One end on the emitter side of 0 is set to zero potential.

The other terminals of the variable capacitance diodes 409 and 410 are
Positive and negative control signals with mutually inverted polarities are applied from the control signal generation circuit 403, respectively.

Now, when the absolute value of the control signal becomes small, the capacitance of the variable capacitance diode of the delay line becomes large, and the frequency band of the delay line becomes narrow.

However, at this time, the high frequency compensation diode 409,
By increasing the capacity of 410, the high frequency range can be more compensated as shown in FIG. 4A.

Figure 4 A is f. -fl, where A is the frequency characteristic of the delay line, B is the high-frequency compensation characteristic of the common emitter amplifier circuit, and C is the frequency characteristic of the delay line.
shows the frequency characteristics of the variable delay line when high-frequency compensation is performed on the delay line output.

Conversely, when the absolute value of the control signal becomes large, the capacitance of the variable capacitance diode of the delay line becomes small, and the frequency band of the delay line becomes wide.

At the same time, the capacitance of the diode for high-frequency compensation becomes small, so that the high-frequency range is not compensated very much, as shown in the opening of FIG.

Figure 4 O6maf. >fl. In this way, the necessary frequency band f1 of the signal whose frequency characteristics are to be delayed is
Compensation can be made to even out the situation.

The output of the emitter-grounded amplification circuit 405 passes through an emitter follower 406 and is taken out from the terminal 4B.

As described above, the present invention compensates for the decrease in frequency characteristics near the frequency band of the delay line in response to changes in the frequency band of the delay line due to changes in the control signal, regardless of the delay time. The frequency characteristics can be flattened to the required band of the signal to be delayed.

Furthermore, since the delay line control signal is used as a signal for performing high frequency compensation, the configuration can be extremely simple.

[Brief explanation of drawings]

FIG. 1 is a wiring diagram of a conventional variable delay circuit, FIG. The mouth is its frequency characteristic diagram. 401... Impedance conversion circuit, 402.
... Variable delay line, 404 ... Impedance conversion circuit, 405 ... Emitter grounding amplification circuit, 403 ... Control signal generation circuit, 409, 4
10... Variable capacitance diode.

Claims (1)

[Claims] 1 a delay line consisting of an inductance and a first variable capacitance element, a control signal generation circuit for controlling the delay time by changing the capacitance of the variable capacitance element, and a second variable capacitor for high frequency compensation at the emitter terminal. It is characterized by having a common emitter amplifier circuit that connects one end of the capacitive element and applies a control signal from the signal generation circuit to the other end of the second variable capacitive element to change the amount of high-frequency compensation. variable delay circuit.