JPH0520927B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] The phase of the input signal is adjusted to a desired phase using a field effect transistor and a parallel tuning circuit using a variable capacitance diode, and the phase of the input signal is adjusted to a desired phase at several 100 MHz.
This can be applied to the optimum phase control of the above-described high-speed clock signal.

[Industrial application field]

The present invention relates to a phase shift circuit for adjusting the phase of a signal such as a high speed clock signal.

In the digital signal transmission system, received pulses are identified using a regenerated clock signal, but in order to minimize identification errors, it is necessary to set the identification timing to the center of the received pulse. Therefore, a phase adjustment circuit is required to adjust the time position of either the equalized output signal, which has been equalized and amplified so that the received signal waveform can be easily identified, or the reproduction clock signal for identification.

A phase shift circuit is used as such a phase adjustment circuit, and it is relatively easy to adjust the phase in low-speed digital signal transmission systems, but in high-speed digital signal transmissions such as optical digital signal transmission systems. Since this method adjusts the phase of a high-speed signal, the configuration is complicated. Therefore, it is desired to be able to adjust the phase of a high-speed signal stably and with a simple configuration.

[Prior art] The simplest configuration of a conventional phase shift circuit is as follows.
A configuration using a coaxial cable is known. This phase shift circuit uses a coaxial cable as a delay line, and by adjusting its length, the signal phase is adjusted. Although the length can be shortened by cutting the coaxial cable, It is difficult to make it longer.

Furthermore, the conventional phase shift circuit shown in FIG.
By combining 11 to L15 and capacitors C11 to C14 to approximate the characteristics of a coaxial cable, using resistor R as a terminating resistor, and selecting input taps T1 to T4, the signal phase from the output terminal OUT is adjusted. The configuration is such that the input/output impedance matching does not deteriorate even when input taps T1 to T4 are selected.

In addition, the conventional phase shift circuit shown in FIG.
21 to L1n and capacitors C21 to C2m are combined to approximate the characteristics of a coaxial cable in the same way as the conventional example described above, and by changing the values of each element or changing the number of elements, input from the input terminal IN and output. This adjusts the signal phase output from the terminal OUT.

The conventional phase shift circuit shown in FIG. 6 is composed of a variable capacitance diode 33 and a transistor 32, where 31 is an input terminal, 34 is a variable resistor, and 3 is a variable capacitance diode.
5 is the output terminal, C31 and C32 are the capacitors, R
31 to R35 are resistors, and +V and -V are power supply voltages.

The base of the transistor 32 is connected to the input terminal 31, the collector is connected to a +V power supply via a resistor R31, the emitter is connected to a -V power supply via a resistor R32, and a capacitor C31 connected to the collector is connected to a variable power supply. A circuit including a capacitive diode 33, a capacitor C32, and a resistor R33 connected to the emitter is connected to an output terminal 35.

By adjusting the voltage applied to the variable capacitance diode 33 using the variable resistor 34, the capacitance can be varied.
Assuming that the capacitance of is C, the resistor R33 connected between the emitter of the transistor 32 and the output terminal 35 is R, and the resistors R31 and R32 are equal values, the voltage transfer function T of this phase shift circuit is T=jX -R/jX+R. However, X=1/ωC. Therefore, if the absolute value of the voltage transfer function T is 1, then ∠T=-2tan ^-1 I understand.

[Problem that the invention seeks to solve]

Conventional phase shift circuits using coaxial cables have the disadvantage that phase adjustment is not easy because the length of the coaxial cable must be adjusted by cutting it, and it is necessary to solder the circuit or connector each time it is cut. There is.

In addition, the conventional phase shift circuits shown in FIGS. 4 and 5 have the disadvantage that high frequency characteristics are not good because they approximate distributed constant circuits with lumped constant circuits. , soldering is required for each selection of input taps T1 to T4, and also in FIG.
Since soldering is required every time the number of elements or element values is changed, phase adjustment is not easy.

In addition, in the conventional phase shift circuit shown in FIG.
Although the voltage applied to the variable capacitance diode 33 can be continuously changed by the variable resistor 34,
Since the Si bipolar transistor 32 is used, there is a drawback that sufficient operation cannot be expected at frequencies of several 100 MHz or more.

An object of the present invention is to enable desired phase adjustment even for signals with frequencies of several 100 MHz or higher.

[Means for solving problems]

The phase shift circuit of the present invention uses a field effect transistor and a parallel tuning circuit, and will be explained with reference to FIG.

The source and drain of a field effect transistor 2 whose gate is connected to the input terminal 1 are connected to one and the other terminals (-
V, +V) and connect the drain to the output terminal 5.
A parallel tuned circuit 6 consisting of a variable capacitance diode 7 and a coil 8 is connected between the source and the output terminal 5, a resistor 9 is connected between the source and one terminal (- The value of the resistor 4 connected between the drain and the other terminal (+V) of the power supply is made larger than that of the resistor 3 connected between the drain and the other terminal (+V) of the power source.

[Effect]

If the mutual conductance of the field effect transistor 2 is gm, the resistors 3, 4, and 9 are R ₁ , R ₂ , R ₃ , and the reactance of the parallel tuned circuit 6 is jX, then the voltage transfer function T is T=jXR ₁ −R ₂ R ₃ /jXR ₁ (1+1/R ₁ gm)+1/gm
(R ₁ +R ₂ +R ₃ ) +R ₁ R ₃ ...(1). Then, if the value of each element is selected so that T=jX−R ₀ /jX+R ₀ (where R ₀ is a constant), the absolute value of the voltage transfer function T will not change due to a change in reactance jX, and the phase will change. only changes.

Furthermore, the following conditions can be obtained from equation (1). That is, R ₁ {1/gm(R ₁ +R ₂ +R ₃ )+R ₁ R ₃ )}=R ₁ R ₂ R ₃ (1
+1/R ₁ gm)...(2) From this formula (2), 1/gm (R ₁ + R ₂ + R ₃ - R ₂ R ₃ /R ₁ ) + R ₁ R ₃ - _{R 2} R ₃ = 0 Therefore, 1/gm(R ₁ R ₃ −R ₂ R ₃ /R ₁ )+1/gm(R ₁ +R ₂ )+
R ₃ (R ₁ −R ₂ )=0 (R ₁ −R ₂ )(R ₃ /gmR ₁ +R ₃ )=−1/gm(R ₁ +R
₂ )<0…(3). That is, for (R ₁ −R ₂ ) on the left side to be negative, the condition R ₁ <R ₂ is required.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a circuit diagram of an embodiment of the present invention, and 11
is an input terminal, 12 and 13 are field effect transistors, 14 is a variable resistor, 15 is an output terminal, 16 is a parallel tuning circuit, 17 is a variable capacitance diode, 18 is a coil, R1 to R11 are resistors, C1 to C7 are capacitors, L1 and L2 are chiyoke coils, +V, -V
is the power supply voltage.

The gate of a field effect transistor 12 is connected to the input terminal 11 via a capacitor C1, and a voltage divided by resistors R2 and R3 is applied as a bias voltage to this gate. This field effect transistor 12 corresponds to the field effect transistor 2 in FIG. A voltage is applied, a parallel tuned circuit 16 is connected between the drain and the capacitor C5, a resistor R7 and a capacitor C3 are connected between the source and the capacitor C5, and the capacitor C5 is connected to the gate of the field effect transistor 13. The drain of this field effect transistor 13 is connected to the output terminal 15 via a capacitor C7. Further, capacitors C2 and C6 are for high frequency bypass.

The resistor R4 and parallel tuning circuit 16 connected to the drain of the field effect transistor 12 correspond to the resistor 4 and the parallel tuning circuit 6 in FIG. 1, and the resistors R5 and R7 connected to the source correspond to the resistor 4 and the parallel tuning circuit 6 in FIG. This corresponds to resistances 3 and 9 in . Therefore, the resistance R4, R
5 is selected to satisfy the relationship R4>R5 from the condition of equation (3).

Further, the field effect transistor 13 has resistors R9, R
The voltage divided by 10 is applied to the gate as a bias voltage, and the drain is applied to the gate coil L.
A voltage of +V is applied to the source through the resistor R11, and a voltage of -V is applied to the source through the resistor R11, forming a buffer circuit for increasing the load impedance of the field effect transistor 12.

The parallel tuned circuit 16 includes a variable capacitance diode 17
The variable capacitance diode 17 includes a coil 18 and a DC cut capacitor C4.
A voltage of +V is applied via the choke coil L1, and a direct current path is formed via the resistor R8 and the variable resistor 14, so the variable resistor 14 adjusts the voltage applied to the variable capacitance diode 14 to increase its capacitance. C can be adjusted.

By setting the voltage transfer function T between the input terminal 11 and the output terminal 15 as T=jX−R ₀ /jX+R ₀ (where R ₀ is a constant) as described above, the capacitance of the variable capacitance diode 17 is By changing C, only the phase can be changed without changing the absolute value of the voltage transfer function T.

Furthermore, since the parallel tuned circuit 16 is constructed using not only the variable capacitance diode 17 but also the coil 18, the change in gain due to variations in the mutual conductance gm of the field effect transistor 12 is as follows.
This is smaller than when a series tuned circuit is used. That is, as shown in FIG. 3, when a series tuned circuit is used, the curve b shows the gain, and the gain |T| changes greatly with a slight change in gm. On the other hand, as in the present invention,
When a parallel tuning circuit is used, the curve a shows a curve a, and the change in gain |T| is small even when gm changes. Furthermore, by using a tuning circuit, the reactance can be changed to positive or negative, so the amount of change in phase can be increased.

〔Effect of the invention〕

As explained above, in the present invention, the resistor 3 (R _{1 ) connected to the source of the field effect transistor 2 and the resistor 4 (R 2 )} connected to the drain are arranged so that R ₁ <R ₂
A parallel tuning circuit 6 is connected to the drain, and by using a field effect transistor 2 for high frequency such as GaAs, it is possible to
It is possible to stably adjust the phase of high frequency clock signals of Hz or higher. Further, by using the parallel tuning circuit 6, the change in gain due to variations in the mutual conductance gm of the field effect transistor 2 becomes small, so that a phase shift circuit with desired characteristics can be easily realized.

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a circuit diagram of an embodiment of the invention, Fig. 3 is a diagram illustrating change in gain due to variation in gm, Figs. 4, 5, and 6 are A conventional phase shift circuit is shown. 1 is an input terminal, 2 is a field effect transistor,
3, 4, and 9 are resistors, (R ₁ , R ₂ , R ₃ ), 5 is an output terminal, 6 is a parallel tuning circuit, 7 is a variable capacitance diode, and 8 is a coil.

Claims (1)

[Claims] 1. One and the other terminals of a power source are connected to the source and drain of a field effect transistor 2 whose gate is connected to the input terminal 1 via resistors 3 and 4, respectively, and the drain and the output terminal 5 are connected to each other. A parallel tuned circuit 6 consisting of a variable capacitance diode 7 and a coil 8 is connected between the source and the output terminal 5, and a resistor 9 is connected between the source and one terminal of the power source. A phase shift circuit characterized in that a resistor 4 connected between the drain and the other terminal of the power source has a larger value than a resistor 3 connected between the drain and the other terminal of the power source.