JPS5936769B2 - Clock signal distribution method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clock signal distribution method for distributing, for example, a clock signal for operating a computer to logic devices inside the computer.

First, the conventional clock signal distribution method J method will be explained using FIG.

In FIG. 1, 1 is a clock signal oscillator, CO is a basic clock signal oscillated from clock signal oscillator 1, and DLI
DL2 is a delay element (
(hereinafter abbreviated as delay line) C1 and C2 are basic clock signals CO output from delay lines DLI and DL2.
2 and 3 are distributed clock signals C1,
A logic circuit operated by C2, 1 is a logic function device (hereinafter abbreviated as a unit) in which a clock signal oscillator 1 consisting of a crystal oscillator is implemented, 2 is a delay line DLI, a unit including the logic circuit 2, and 3 is a delay line. Line DL2
, a unit including a logic circuit 3. By the way, the distributed clock signals C1 and C2 are sent to the inside of the computer via signal lines, but if a large number of logic circuits to which the signal lines are input are physically distributed within the computer, the clock signals are affected by the wiring length of the signal lines. This results in a so-called phase mismatch state in which a shift occurs between the phases of the set timings.

This causes malfunction of the cumulative calculator and reduces reliability. When performing phase alignment between the distributed clock signals C1 and C2, conventionally a delay line is connected to the distributed clock signal for each unit, and each distributed clock signal C1,
A clock signal distribution method was adopted that required adjustment for each unit so that the phase shift between C2 was minimized. However, in general, a large number of clock signals are used in a computer, and as the computer becomes larger, the units to which the clock signals are distributed are dispersed, and the phase difference between each clock signal is measured at each measurement point of the distributed unit. Adjusting everything requires a lot of effort and increases the adjustment time.

The present invention aims to improve these conventional problems, and will be described in detail below with reference to FIG. 2. In FIG. 2, the same reference numerals as in FIG. 1 indicate the same or corresponding parts. DL3
, DL4 are delay lines that delay the basic clock signal CO; C1 and C2 are clock signals distributed to each unit from the delay lines DL3 and DL4; 4 and 6 are echo clock signals C3, 6 in synchronization with the input basic clock signal CO; Input gates that send C4 to corresponding units K5 and K6; C3 and C4 are the input gates 4 and
6 to corresponding units K5, K6 and returned to output gates 5, 7 corresponding to the input gates 4, 6, respectively; Output gate, A, B
are the output points of the output gates 5 and 7, K4 is the clock signal oscillator 1 consisting of a crystal oscillator, and the delay line D is
A unit K5 including L3, DL4, input gates 4, 6, and output gates 5, 7 is a logic circuit 2 and a distributed clock signal C1.
, a unit including an echo clock signal C3, K6 is a logic circuit 3, a distributed clock signal C2, an echo clock signal C
This is a unit containing 4. Here, for convenience of explanation, it is assumed that there are two distributed clock signals.

In such a circuit, the basic clock signal CO is now received by each input gate 4, 6, reaches the corresponding unit K5, K6 as an echo clock signal C3, C4, respectively, and is applied to the corresponding output gate 5, 7, respectively. When the signals are returned, the phase difference between the output points A and B of the output gates 5 and 7 is such that the delay times of these input gates 4 and 6 and output gates 5 and 7 are equal, and the echo clock signals C3 and C4 are transmitted. If the delay time of the signal line is uniform, this will be twice the phase difference between the clock signals measured at the turning point, that is, at the input of units K5 and K6. That is, the returned echo clock signals C3 and C4 are measured at the output points A and B, and the delay line DL3D is adjusted so that they match at 1/2 of the phase difference.
By adjusting L4, the phase difference between units K5 and K6 can be matched. In this invention, as described above, the echo tallock signal is sent to the corresponding unit in combination with the distribution clock signal, and the return is centrally measured and adjusted to match the phase difference of the distribution clock signal between each unit. Can be done.

According to the present invention, there is no need to extend the probe of a measuring instrument such as an oscilloscope to the distribution destination of the clock signal at the time of adjustment, and the echo clock signal for adjustment is stored in advance in a system such as a computer. Since this is achieved using built-in means, there is no need to install special cables during adjustment.
All work related to the measurement and adjustment of the distributed clock signal can be performed centrally at the side distributing the clock signal. In addition, even if an oscilloscope or the like is used during measurement work, the probe used can be short and there are no errors introduced due to its length, which has significant practical effects. be. Therefore, since it is not necessary to measure the clock signal for phase control for each distributed unit, the adjustment process and its time can be shortened.

[Brief explanation of drawings]

FIG. 1 is a block diagram for explaining a conventional computer clock signal distribution system, and FIG. 2 is a block diagram showing an embodiment of the present invention. In the figure, CO is a basic clock signal, and Cl and C2 are distribution clocks. Signals, C3 and C4 are echo clock signals, A and B are output points of output gates 5 and 7, K
1 to K6 are logic function devices, DL1 to DL4 are delay elements,
1 is a clock signal oscillator, 2 and 3 are logic circuits, 4 and 6 are input gates, and 5 and 7 are output gates.

Claims (1)

[Claims] 1 A clock signal oscillator that generates a basic clock signal, a plurality of delay elements that generate distributed clock signals from the basic clock signal oscillator to corresponding units, and a plurality of delay elements corresponding to each of the plurality of delay elements. The echo clock signal is obtained by making the basic clock signal go back and forth twice from the input gate to the corresponding unit and returning to the output gate, which is generated from the delay element. A clock signal distribution method characterized in that phase matching between a plurality of distributed clock signals is performed using the echo clock signal.