JPS5937511B2 - character pattern generator - Google Patents

Description

[Detailed description of the invention] The present invention relates to a character pattern generating device.

A pattern memory is often used as a character pattern generator, which outputs a character pattern corresponding to input of a character code. In particular, when a character pattern is a Kanji pattern, there are a large number of character types, so a large-capacity memory such as a magnetic disk is required. However, when a magnetic disk is used, it takes a long time to access, so the pattern generation speed is low. For this reason, a large capacity memory such as a magnetic disk (first character pattern memory) stores many character patterns that are relatively infrequently used, while decimal characters that are generally used frequently are stored in a large capacity memory such as an IC memory (second character pattern memory). By storing the pattern in a character pattern memory (character pattern memory), it is possible to improve the apparent pattern generation speed. That is, the second character pattern memory is first searched to see if the character pattern corresponding to the input character code exists, and only when the character pattern does not exist is read out from the first character pattern memory. At this time, the character patterns read from the first character pattern memory are stored in the second character pattern memory, and the least frequently used ones that have been in the second character pattern memory are removed. Through software management, character patterns that are likely to be used by the user are always kept in the second character pattern memory. However, in practice, data management using software takes a lot of time, and the pattern generation speed cannot be improved as much as expected. This invention was made in view of the above circumstances,
An object of the present invention is to provide a character pattern generation device with improved pattern generation speed.

FIG. 1 shows an embodiment of the present invention.

A large number of character patterns, for example 10,000 characters, are stored in a magnetic disk (MD) 1 (first character pattern memory).

There is also a high-speed read/write memory (DBM) 2 (second character pattern memory) that can accommodate character patterns of, for example, 200 characters, and the DBM 2 stores character patterns read from MDl. 3 is a data reading circuit that reads pattern data from MDl and supplies it to DBM2; 4
is a device that uses the pattern data of DBM2, for example, CPU5.
6 is an index memory (TM) that stores a correspondence table between the character code and the address in the DBM 2 occupied by the corresponding character pattern, and chain child information (to be described later); A register that holds the output character code, 8 is a search circuit that searches whether the character code matching the contents of register 7 is in the correspondence table in TM6, and 9 and 10 are the highest priority correspondence tables in TM6, respectively. registers (FDAR, LDA) that store the address of
R), 11 is a data read circuit in 'RM6, 12 is T
A write circuit for writing data into M6, 13 a data modification circuit, and 14 a control circuit.

FIG. 2 shows the structure of TM6 data. In the same figure, K
EY indicates key data, which is a character code here.
ADD is the address in DBM2 of the character pattern corresponding to the character code indicated by KEY. These KEY,
A correspondence table is constructed by ADD. Also BD and A
D is provided to specify the priority order of the character pattern corresponding to the character code indicated by KEY, and the address of the correspondence table with one higher priority and the address of the correspondence table with one lower priority, respectively. give. Like this TM
The data stored in each address of 6 has a reversible list structure, and the order is such that the most recently used character pattern is placed at the top, and the rest are placed in the order of new use. ing. In other words, TM6
The data has a physical order determined by its address and a order determined by a reversible list structure. If the latter is called a logical order, FDAR9 and LDAR10 indicate which address of TM6 stores the correspondence table corresponding to the highest and lowest logical order, respectively. It is assumed here that the number of data in TM6 matches the number of character patterns in DBM2. Next, the operation of this embodiment will be explained with reference to the flowcharts shown in FIGS. 3a to 3d.

In FIG. 3a, the operation is started by the utilization device CPU 5 outputting the character code KEYc of the desired character pattern (block 100).

This character code KEYc is set in register 7.
In block 101, search circuit 8 checks whether a character code matching the content KEYc of register 7 exists in TM6. That is, the search circuit 8 drives the read circuit 11 to sequentially read the correspondence table from the TM 6, and sequentially compares the KEY part with the contents of the register 7 (Program 1).
02). As a result, if there is no matching character code in all the correspondence tables, the process moves to process A, which will be described later. The flow of process A is shown in FIGS. 3b and 3c. Process A is performed when the desired character pattern does not exist in the DBM2. When the search circuit 8 outputs a mismatch signal, the control circuit 14 reads the contents of the LDARIO (block 103). If the contents of LDARIO are AE, then TM
Address AE 6 stores the lowest ranking correspondence table. Next, in block 104, the contents of LDARIO are supplied to the readout circuit 11, and the readout circuit 11 sends the data at address AE of TM6 to the data modification circuit 13 via the readout control circuit 14. Address AE that was just read
data is drawn in block 104. On the other hand, the control circuit 14 sends the contents KEYc of the register 7 to the data reading circuit 3, and causes the character pattern corresponding to the character code KEYO to be read out from MDl. This character pattern is DBM
2 is written to address ADDE (block 105).
. Address ADDE is the content of address AEOADD part of TM6 that was read earlier. Next block 10
6, the control circuit 14 controls the data B of the address AE.
The content BDE of the D part is sent to the reading circuit 11, and the data at the address BDE is read from TM6. This data is shown inside block 106. This data is sent to the data modification circuit 13, and its AD part is changed to ADE indicating the lowest position in the correspondence table. This corrected data is shown inside the button 107. This modified data is written to the same address BDE of TM6 via write circuit 12 (block 107).Next, in block 108, control circuit 14 writes BDE to LDARIO. That is, this time it is displayed that the lowest correspondence table is accommodated at address BDE. In block 109, control circuit 1
4 reads the contents As of FDAR9 and executes the block 110.
The read circuit 11 reads the data at address As of TM6 at
Read through.

In the next block 111, the control circuit 14
Write the content AE of LDARIO that was read earlier. The data modification circuit 13 changes the KEY part of the data at the address AE read in the block 104 to the input character code KEYc, and changes the BD part to the address As(7) read out in the block 110.The contents of the BD part BD
s and sends it to the write circuit 12.

Thus, the data shown inside block 112 is written to address AE of TM6. Next, data correction circuit 1
3 changes the BD part of the data at address As read out by block 110 to AE. This modified data is written to the same address As via the write circuit 12 (block 113). Also, in block 114, the control circuit 14 drives the data transfer circuit 4 to address DBM.
The character pattern accommodated in ADDE No. 2 is transferred to the CPU 5 and the processing is completed. The flow of process B is shown in FIGS. 3D and 3e.

Process B is performed when the desired character pattern exists in the DBM2. At this time, the search circuit 8 sends a match signal to the control circuit 14. Assuming that the data at the address AK of TM6 includes the character code KEYc, this data is sent to the control circuit 14 (block 115). The Sakyo circuit uses the contents A and A of the BD part of the data at address AK.
Using the content AI of part D, address AJ from TM6
and AI data is read out (block 116). Next, read the contents As of FDAR9 (block 117),
Read the data at address As of TM6 (Proc 1
18). In block 119, the read data at addresses AK, AJ, AI, and AS is transferred to the data correction circuit 1.
3, and the modified data is written to TM6 again via the write circuit 12. At this time, address A
In the data of K, the BD part and AD part are each B.
The data becomes Ds and As and becomes the highest level data. Address A
For the data of J, the AD part is changed to AI. The BD part of the data at address AI is changed to AJ. The BD part of the data at address As is changed to AK.
Then, AK is written to FDAR9. Next, at block 120, the character pattern at address ADDK of DBM2 is transferred to CPU5, and the process is completed. As described above in detail, according to the present invention, the TM data structure is a reversible list structure, so management of the correspondence table is possible only by changing the chain elements, and it does not take much time.

In particular, when the character pattern generator is accessed according to normal Japanese sentences (including Kanji), 70% of the accesses are to characters within the top 200 most frequently used characters. According to the present invention, the top 200 most frequently used characters at the time are registered in the DBM according to the usage status, and the probability that the character pattern to be accessed is registered in the DBM is more than 80%. ing. In other words, the speed at which character patterns are generated is four to five times faster than when only disks are used.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of the invention, FIG. 2 is a diagram showing the data structure of an index memory used in an embodiment of the invention, and FIGS. 3a to 3e are diagrams showing an example of the invention. It is a flowchart for explaining the operation of the embodiment. 1... Magnetic disk, 2... Read/write memory, 5... CPU, 6... Index memory, 8... Search circuit ,9,10
...Register, 13...Data correction circuit, 14...Control circuit.

Claims (1)

[Claims] 1. It has first and second character pattern memories that store character patterns, and an index memory that stores a correspondence table between the address of the character pattern stored in the second character pattern memory and the character code, and When the index memory is searched from the code and the character pattern corresponding to this input character code does not exist in the second character pattern memory, the character pattern is transferred from the first character pattern memory to the second character pattern. In a device configured to be read after being transferred to a memory,
means for storing chain child information representing the relative order between the correspondence tables to indicate the priority order of the correspondence tables; first address holding means for holding the address of the correspondence table having the highest priority; A second address holding means for holding an address of a correspondence table having the lowest priority, and a means for changing the correspondence table and chain child information, and a correspondence table corresponding to the input character code exists in the index memory. If not, change the character code of the correspondence table of the address indicated by the second address holding means to the input character code, and write the contents of the second address holding means to the first address holding means. A character pattern generator featuring: