JPS593755B2 - electronic musical instruments - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for adjusting the pitch of a musical tone generated when two different keys are pressed in sequence by adjusting the pitch corresponding to one key (hereinafter referred to as the first operation key). frequency) to the other key (hereinafter,
Regarding an electronic musical instrument in which a portamento performance sound effect or a glitsando performance sound effect can be obtained by changing the pitch (frequency) continuously or stepwise to a pitch (frequency) corresponding to a second operation key, During the pitch change process from the first operation key to the second operation key of a sound effect or a glitsand performance sound effect, the pitch is temporarily raised or lowered to a value that exceeds the pitch of the second operation key. This invention relates to an electronic musical instrument having an overshoot function that controls the pitch to return to the pitch of the second operation key after that.

o In recent years, with the rapid development of electronic technology, various electronic musical instruments have been developed, and electronic organs, which are representative of electronic musical instruments, are capable of producing many tones and various sound effects, making them ideal for musical expression. It is widely used as an instrument that can produce a wide range of sounds and is relatively easy to play, even for beginners.

In this case, in conventional electronic musical instruments, the pitch is changed continuously or stepwise from the pitch corresponding to the first operation key to the pitch corresponding to the second operation key to produce a portamento performance sound or a gris sando. Function to generate performance sound effects 9
is provided. However, the portamento or glitsando function provided in conventional electronic musical instruments simply changes the pitch of the generated musical tone from the pitch corresponding to the first operating key to the pitch corresponding to the second operating key in a continuous or stepwise manner. Therefore, the portamento performance sound effect or the glissando performance sound effect was monotonous and had little variation.

An object of the present invention is to provide an improved electronic musical instrument that can produce new portamento performance sound effects or glissando performance sound effects that cannot be obtained with conventional electronic musical instruments.

Another object of the invention is to provide an electronic musical instrument that emphasizes the end of a portamento or glissando sound effect.

In order to achieve such an object, the electronic musical instrument according to the present invention includes, in the process of changing the pitch of the generated musical tone from the pitch corresponding to the first operating key toward the pitch corresponding to the second operating key. , the pitch is given a characteristic (hereinafter referred to as an overshoot characteristic) in which the pitch is temporarily raised or lowered to a value exceeding the pitch of the second operation key, and then returns to the pitch of the second operation key. It is something.

Hereinafter, the electronic musical instrument according to the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram schematically showing the overall configuration of an embodiment of an electronic musical instrument according to the present invention, and shows the main structure of the electronic musical instrument according to the present invention. a key coater 100 that detects an operated key switch (closing operation in the case of a make contact, opening operation in the case of a break contact) and generates a signal (key information) representing the detected key switch, that is, a key code KC; A channel processor 200 that assigns the key code KC supplied from the key coater 100 to one of the channels (much fewer than the number of keys) that can be sounded simultaneously; and a channel 5 channel processor 2.
A key code conversion unit 300 that processes the key code KC supplied via 00 and converts it into a key code KC'' for obtaining a glissando effect or a portamento effect.
The key code supplied from the key code converter 300 is a key code that generates the pitch voltage KV corresponding to 5KCI, the pitch voltage converter 400, and the operation assigned to the valley channel by the channel processor 200. The above-mentioned tone high voltage KV corresponds to the key press and release of the key switch.
A tone forming section 600 that generates musical tone signals corresponding to the tone high voltages KV supplied from each channel of the channel-specific tone high voltage control section 500 for each channel. , a pitch voltage control section 700 that controls the channel-by-channel pitch voltage control section 500 to control switching between glitsando and portamento and its speed, and a timing signal generation section 800 that supplies various timing signals to each section described above. It is configured.

In the key coater 100, a large number of key switches 10
A key switch circuit 102 having 1a to 101n is provided, and each key switch 101a to 101n of this key switch circuit 102 is divided into a plurality of blocks (for example, a group for each octave), and each key switch in each block is divided into a plurality of blocks. notes (e.g. C,
C., D. . . . B key), and one terminal (movable contact) of each key switch 101a to 101n.
The a side is commonly connected to the same notes of each block to draw out the wiring N, ~Nm for each note, and the other terminal (fixed terminal) b side is commonly connected to each of the same blocks to draw out the wiring B, for each block. ~ Bt is out.

Therefore, in this key switch circuit 102, each key switch 101a is connected between each matrix at each intersection of a matrix (matrix wiring) in which the block wirings B, .about.Bt are "rows" and the note wirings N, .about.Nm are "columns." .about.101n are connected to each other. As a result, the total number of wires drawn out from the key switch circuit 102, that is, the total number of wires of the block wires B, ~Bt and the note wires N1 to Nm, is much smaller than the number of all the key switches 101a to 101n. ing. For example, all key switches 1
Assuming that the number of 01a to 101n is "Txm",
In this case, the total number of wires drawn out from the key switch circuit 102 is the number of blocks t+the number of notes m, and the number is "
m+t" book. Each key switch 101a to 101n of the key switch circuit 102 configured in this way is connected to a note detection circuit 103 via note wirings N1 to Nm, and to a block detection circuit 104 via block wirings B1 to Bt. has been done. In this case, the detection of all operating key switches among all the key switches 101a to 101n is completed by sequentially executing several detection operation states (hereinafter simply referred to as states).

The first state (STl) is the note detection circuit 103
Apply a signal to the movable contact side a of all the key switches 101a to 101n via the notebook wiring N, to Nm,
The applied signal is derived through the fixed contact side b of only the operating key switch to the block wirings B1 to Bt of the block to which the operating key switch belongs, and the derived signal is supplied to the block detection circuit 104 and stored.
This will tell you which procs are running (turned on).
The presence of one or more key switches is detected. Note that the storage timing of the block detection circuit 104 in this first state is determined by the state control circuit 105 operating in synchronization with the timing signal generation section 800.
The first state signal is determined by the first state signal provided by the first state signal.
When the storage operation of block detection circuit 104 is completed, state control circuit 105 detects this and controls the second state. Next, in the second state (ST2), the block (
push out one proc (one proc or multiple procs) according to a predetermined priority order,
Applying a signal to the fixed contact b side of each key switch included in the block through the block wiring B, ~Bt corresponding to the block extracted from the block detection circuit 104,
As a result, the signal is derived from the note wirings N1 to Nm on the movable contact a side of the key switch of each note in the block and is stored in the note detection circuit 103. In this way, the signal from the block detection circuit 103 will be transmitted only to the note wirings N1 to Nm corresponding to the key switches 101a to 101n in operation, and this signal will be stored in the note detection circuit 103. Therefore, the note of the operating key switch (one or more) in the extracted block will be detected. Further, the block signal extracted by the block detection circuit 104 contains multiple bits (in this case, 3 bits) representing the block.
(bit) into a block code signal (hereinafter referred to as block code BC), which is supplied to the sample and hold circuit 106 and stored. Note that the one-block extraction timing of the block detection circuit 104 and the storage timing of the note detection circuit 103 in this second state are as follows.
As in the case of the first state described above, the state control circuit 1
It is determined by the second state signal supplied from 05. When the storage operation of the note detection circuit 103 is completed, the state control circuit 105 detects this and controls the third state. Next, the third state (ST,) is an operating state following the second state, in which the note (one or more) stored in the note detection circuit 103 is synchronized with the system clock. , and are extracted sequentially according to a predetermined priority order, and the extracted note signals are converted into a note code signal (4 bits in this case) of multiple bits (4 bits in this case) representing the note.
Hereinafter, the note code is converted into a note code NC) and sequentially supplied to the sample and hold circuit 106.

Since this third state is executed only for notes stored in the note detection circuit 103, no time is wasted. For example, if three types of notes are stored in the note detection circuit 103, the third state regarding a certain block will be completed in three clock times. When all the note code signals stored in the note detection circuit 103 are read out, the state control circuit 1
05 detects this and controls to the next state. In this case, if the block signal is still stored in the block detection circuit 104, control returns to the second state and the third state, and these states are executed in the same manner as described above. In addition, if there is no memory of a block signal in the block detection circuit 104, the charges remaining in the block wirings B1 to Bt of the key switch circuit 102 (the stray capacitance of the wiring or the minute capacitors connected to the valley wirings) After all the charges are discharged and set, the state returns to the first state. On the other hand, the sample and hold circuit 106 stores and holds the block code BC supplied from the block detection circuit 104 in the second state, and is synchronized with the note code NC supplied from the note detection circuit 103 in the third state. and output.

Therefore, the sample and hold circuit 106 sends out a key code KC having a 7-bit configuration in which a block code BC and a note code NC are combined, and the operating key switch can be easily identified by this key code KC. can do. In this way, the first state (S
T, ← 2nd state (ST2) → 3rd state (ST,
), etc., or when the block detection circuit 104 sends out the block codes BC for all the blocks initially stored and finishes sending out the note code NC for the note of the operating key switch in the last block, Since all of the memories in the block detection circuit 104 and the note detection circuit 103 are extracted and completely erased, this causes the fourth state (STO entry, that is, a standby state).

Then, the key switch circuit 102 and the note detection circuit 10
After confirming that all operations of 3 and the block detection circuit 104 have been reset, the state returns to the first state (ST,).
After that, as mentioned above, the second state (ST2
), the third state (ST, ) is repeated to reach the fourth state (STO), that is, the waiting state.
The detection operation for all key switches is repeated once. The key code KC sent out from the sample hold circuit 106 of the key coater 100 is supplied to the channel processor 200, where it is assigned a channel that forms a musical tone signal.

In this case, the key code KC sent from the sample and hold circuit 106 is held for a certain period of time, and this holding time corresponds to the operating time during which one assignment process is executed in the channel processor 200. In addition, this key coater 100 converts all of the operation key switches into corresponding key codes KC and converts the start signal and send it.

This signal X is used in channel processor 200 for key-off detection. In addition, this key coater 1
Block code B of key code KC sent from 00
Table 1 shows an example of the contents of C and note code NC.

Next, the channel processor 200 includes a first key code memory 201, a key on/off detection circuit 202, a truncate circuit 203, and a key press state memory 204.

The first key code memory 201 is provided with a specific number of storage circuits corresponding to the number of channels that can be sounded simultaneously, and this storage circuit is advantageously constructed of a circular shift register. In this case, if the number of channels is A1 and the number of bits of key code KC is B, A
A stage (1 stage = B bits) shift register is used, and the stored (already assigned) key code KC is sequentially shifted by a clock pulse and sent out in a time-division manner to control the generation of musical waveforms. It is used as a signal and is fed back to the input side of this shift register for circulation. The key-on/off detection circuit 202 compares the input key code KC supplied from the key coater 100 with all stored key codes KC sequentially sent out from the first key code memory 201 in a time-sharing manner, and if they match, the input key code KC is A key code KC identical to the code KC is assumed to have already been assigned to a certain channel, and is prevented from being stored in the first key code memory 201, that is, the channel assignment is stopped.

Furthermore, if the above comparison results do not match, it means that a new key has been operated, so this input key code K
C is stored in all empty channels of the first key code memory 201. Furthermore, if the above comparison results do not match and the key code KC is assigned to all channels, the truncate circuit 203 assigns the note whose attenuation has progressed the most among the notes that have already been released. Detect the channel that is being played, and input the key code KC stored in this channel. - Control to forcibly rewrite code to KC. The key-on/off detection circuit 202 also stores the assignment state of the input key code KC to each channel in the key press state memory 202 each time.
4 to be stored, and its read output is used to control the sound generation operation of the valley chi yannel (described later), as well as to detect key release and change the corresponding memory contents of the key press state memory 204. The sound generation of the channel is terminated while complying with predetermined conditions, that is, while performing control such as gradually attenuating it. In the subsequent operation, an empty channel is selected from the contents stored in the key press state memory 204, and the input key code KC is stored in the stage of the corresponding channel in the first key code memory 201. Note that the first key code memory 201 and key press state memory 204
The signals are stored by selecting portions corresponding to each channel in a time-division manner in synchronization with each other. Next, only when a control signal is supplied to the key code shift control terminal 301, the key code conversion section 300 processes the key codes KC sequentially supplied from the channel processor 200 to convert the key codes KC into a predetermined range, that is, when a certain operation is performed. A key code KC'' that is sequentially shifted (including addition and subtraction) under certain conditions while overshooting by a predetermined value over the range from the key code KC corresponding to the next operated key to the key code KC corresponding to the next operated key. This is the part that converts the key code KC'' to obtain a glissando effect or a portamento effect having overshoot characteristics.

The key code conversion unit 300 is configured with a key code shift control terminal 301 and a cyclic shift register having storage stages equal to the number of channels, and converts the key code K supplied from the channel processor 200.
The output key code K of the second key code memory 302 is only when a control signal is supplied to the key code shift control terminal 301.
Calculated key code KC obtained by adding or subtracting a predetermined value to C
' again in the second key code memory 302. In this key code conversion section 300, the first
Key code KC supplied from key code memory 201
is input, and the pitch change direction is determined by comparing the key code KCl corresponding to the first operation key and the key code KC2 corresponding to the second operation key to determine the direction of pitch change when performing portamento or grissando. circuit 304
The addition and subtraction processing in the arithmetic circuit 303 is selectively controlled by the discrimination output. The key code converter 300 is also provided with a preset switch 305 that presets the overshoot amount for the second operation key pitch as a digital amount. The output value of this preset switch 305 is summed with the key code KC supplied from the first key code memory 201 in an adder 306, and the sum of the key code KC supplied from the first key code memory 201 is obtained in a subtracter 30r.
The difference from C is required. Therefore, the adder 306 outputs the upper limit value of the overshoot in the rising direction of pitch during portamento or glissando performance, and the subtracter 307 outputs the lower limit value of the overshoot in the descending direction. The upper limit value output from the adder 306 and the lower limit value output from the subtracter 307 are compared with the output key code KC'' of the second key code memory 302 in first and second comparators 308 and 309, respectively. , when the two match, the arithmetic operation of the arithmetic circuit 303 is reversely controlled, that is, the addition state is switched to the subtraction state, and the subtraction state is switched to the addition state. When the coincidence output is sent out, the arithmetic circuit 303 performs an operation to shift the key code KCI from the upper or lower limit value of the overshoot toward the key code KC corresponding to the second operation key pitch. In this way, the arithmetic circuit 303
The calculation operation of the first comparator 308 or the second comparator 309
After switching by the coincidence output of
03 is the second key code supplied from the first key code memory 201.
The matching output of the third comparator 310 that detects matching between the key code KC2 corresponding to the operation key and the output key code KC'' of the second key code memory 302 is taken in with priority, and the calculation operation is performed based on this matching signal. The state in which the calculation operation of the calculation circuit 303 is stopped in this way means that the generation of the portamento sound effect or the glitsando sound effect having overshoot characteristics has finished and the pitch corresponding to the second operation key (key code KC, Note that the arithmetic circuit 303 shifts the key code KC, which is composed of a binary code (BCD) in which one unit is a semitone, as shown in Table 1 above. Due to the familiarity,
It is necessary to change the amount of one shift depending on whether the scale in the shift direction is a semitone or a whole tone. The code detector 311 controls this shift amount, and this code detector 311 determines the contents of the output key code KC'' of the second key code memory 302 and calculates the addition value or subtraction value of the arithmetic circuit 303. In addition, the arithmetic circuit 303
This calculation is performed every time a speed control pulse TC is supplied to the speed control terminal 312 from a pitch voltage control section 700 (described later), and this speed control pulse TC controls the speed of pitch change during portamento or gris sando performance. It is determined. In this way, the key code conversion unit 300 performs arithmetic processing on the key code KC to convert the key code KCl corresponding to the first operation key to the second operation key only when a control signal is supplied to the key code shift control terminal 301. The key code KC corresponding to the second operation key is shifted to a key code KC that exceeds a predetermined value, and then the key code KC corresponding to the second operation key is shifted back to the key code KC. Control is performed in a time-division manner for each channel. By converting the output key code KC'' of the key code converting section 300, which has undergone such arithmetic processing, into a corresponding tone pitch voltage and supplying it to the musical tone shape section 600, the first
A portamento sound effect or a glissando sound effect in which the pitch changes continuously or stepwise while overshooting from the operating key pitch toward the second operating key pitch can be obtained. Next, the key code/pitch voltage conversion section 400 is constituted by a sampling circuit 401, a sampling control circuit 402 that controls the sampling period, and a digital/analog conversion circuit 403.

And this key code. The pitch voltage converter 400 converts the key code KC″ supplied from the key code converter 300
is sampled in the sampling circuit 401, and the sampled key code KCI! Digitally.
The signal is supplied to the analog conversion circuit 403. In this case, the sampling period of the sampling circuit 401 is determined by the output of the sampling control circuit 402, and the period counts one more clocks than the number of channels for shifting the contents of the second key code memory 302. The time has come. Therefore, the sampling circuit 40
1 is to sample key codes KC'' corresponding to different channels in sequence almost every time the shift of the second key code memory 302 completes one cycle, and to continue outputting this sampled key code KC' until the next sampling time. This is how the key coater 100 and channel processor 200 switch the key switch 101a.
~101n states (key pressed state and key released state) need to be detected quickly and assigned to channels, whereas the part that handles the pitch voltage performs high-speed operation because it is processed in parallel. It is not necessary, and the operation cannot follow the analog signal's high voltage when handled at high speed. In other words, the waveform becomes dull due to minute capacitance in the circuit system and wiring system, making it impossible to obtain an accurate tone that matches the key code KC''.For these various reasons, the key code KC' A deceleration sampling is performed to form a deceleration-sampled key code KC'.A digital/analog conversion circuit 403 connected to the output side of the sampling circuit 401 converts the above-mentioned key code KCl into a corresponding tone pitch voltage KV. This digital.
The analog conversion circuit 403 converts the key code KC decelerated and sampled by the sampling circuit 401 as described above.
〃 is input, this key code KC is divided into a block code BCI and a note code NCI, and each is decoded. Then, a voltage signal corresponding to the block is extracted from the resistive voltage divider circuit by the decoded output of the block code BCI, and the voltage signal corresponding to the block is corresponded to the note by the output of the decoded note code NC. By further dividing the pressure, the key code K
A tone pitch voltage KV corresponding to C is generated. This pitch voltage K is distributed to the same channel to which the valley-sampled key code KC of the sampling circuit 401 is assigned, by a control signal supplied from the sampling control circuit 402. In this case, the operation of distributing the tone high voltage KV to each channel operates in synchronization with the key depression state memory 204 described above, and the selected channels also match. Next, the channel-by-channel pitch voltage control section 500 includes pitch voltage control circuits 501a to 501h that are independently provided for each valley channel.

These sound pitch voltage control circuits 501a to 501h are connected to the digital. The tone pitch voltage K supplied from the analog conversion circuit 403 is input for each channel, and the key press state memory 20
The tone pitch voltage KV is stored in a capacitor by opening a gate circuit in response to a key-on signal supplied from 4, and the terminal voltage of this capacitor is sent to a tone forming section 600, which will be described later. Further, each of the tone pitch voltage control circuits 501a to 501h is configured to control a charging time constant of the tone pitch voltage KV to the capacitor by a control signal supplied from a tone pitch voltage control section 700, which will be described later. The sound high voltage KV outputted by this
By changing the rise (fall) of ``, a glitsando effect or a portamento effect is obtained.Next, the tone forming section 60
0 is a musical tone forming circuit 601a provided for each channel.
~601h.

In this embodiment, the tone forming circuits 601a to 601h include a voltage controlled variable frequency oscillator (hereinafter referred to as CO), a voltage controlled variable filter (hereinafter referred to as VCF), and a voltage controlled variable gain amplifier (hereinafter referred to as VCF). ) and an envelope pre-generator (EG) that programs the control timing and control amount of each section (VCO, VCF, VCA). KV''
When supplied, the VCO oscillates at a frequency corresponding to the input sound high voltage KV'. This oscillation output is sent out as a musical tone signal via the VCF and VCA, and after being mixed with the musical tone signal sent out from the musical tone forming circuit in charge of other channels at mixing resistors 900a to 900h, it is sent via the output terminal 901. The signal is supplied to a speaker (not shown).

In this case, by controlling the VCO, CF, and CA with a control waveform signal generated from an envelope generator (EG), the oscillation frequency of the VCO changes slightly according to this control waveform signal, and the frequency characteristics of the VCF change slightly. changes to form a musical tone signal rich in naturalness and musicality, and furthermore, the VCA controls the musical tone envelope according to the control waveform. This envelope generator (EG)
is under the control of an adjustment lever provided on an operation panel (not shown) of the electronic musical instrument, and the control start timing is determined by a key-on signal supplied from a key-press state memory 204. Sound pitch voltage control section 700
By supplying a control signal to each tone pitch voltage control circuit 501a to 501h of the channel-by-channel tone pitch voltage control section 500, the charging time constant for the capacitor provided in each tone pitch voltage control circuit 501a to 501h is determined. is used to switch between gris sando and portamento, and to control changes in pitch voltage during sustain. The timing signal generator 800 counts a reference clock signal (system clock) supplied from a reference oscillator (not shown), generates various synchronization signals, and supplies these synchronization signals to each of the above-mentioned parts to improve overall operation. synchronization has been obtained.

The above description is an explanation of the main part structure and its operation with respect to the block diagram schematically showing the overall structure (FIG. 1) showing one embodiment of the electronic musical instrument according to the present invention.

The structure and operation of each block shown in FIG. 1 will be explained in detail below with reference to a drawing showing a concrete circuit and an operation waveform chart of the main part thereof. Before entering into the description of the concrete circuit, the special use of symbols in the circuit will be explained.

Figures 2a to 2f show examples of symbols used. Figure 2a represents an inverter, B and c represent an AND gate, D and e represent an OR gate, and f represents a delay flip-flop. It represents. In this case, in the above AND gate or OR gate, when the number of inputs is small, the normal display method as shown in B and d of the same figure is adopted, and when the number of inputs is large, the special display method shown in C and e of the same figure is adopted. Adopt a projection method. In Figures C and E, one input line is drawn on the input side of the circuit, multiple signal lines are crossed with this input line, and the signal line of the signal to be input to the circuit intersects with the input line. The points are circled. Therefore, in the case of the example shown in figure c, the logical expression becomes Q=A-B'D, and in the case of the example shown in figure e, the logical expression becomes Q=A+B+C. Figure 3 shows
This is a specific circuit diagram showing the main parts of the timing signal generating section 800 shown in FIG. It is the part that gives rise to life.

Therefore, this timing signal generating section 800 will be explained first. This timing generation section 800 is composed of four flip-flops connected in cascade.
A shift register 8 having a stage counter 801 and bits corresponding to the number of channels (in this embodiment, the circuit will be described below as a circuit having an 8-channel configuration).
It consists of 02. A counter 801 inputs and counts the clock pulse φ shown in FIG. 4A among the output pulses φ1 and φ2 obtained by dividing the output pulse φ of a reference oscillator (not shown) by two. The pulse interval of this clock pulse φ1 is, for example, an extremely high-speed pulse of 1 μs, and this pulse interval will hereinafter be referred to as "channel time". If the number of simultaneous sounds in this electronic musical instrument is 8, the total number of channels is 8, and the clock pulse φ1
The 1 μs wide time slots sequentially separated by
It is driven sequentially corresponding to the first channel to the eighth channel. This is because the aforementioned channel processor 200 has a dynamic logic structure in which various storage circuits and logic circuits are shared in a time-division manner in order to be able to generate a plurality of musical tones simultaneously. Furthermore, the above-mentioned channel times are generated by cycling every 8 channel times, assuming that each time slot is sequentially designated as the 1st channel time to the 8th channel time as shown in FIG. 4b. Become. In other words, the counter 801
When a clock pulse φ1 is supplied from an oscillator (not shown) to the input terminal of the counter 801, the counter 801 sequentially counts the clock pulse φ1 and outputs the count result as a binary-decimal code having a parallel 4-bit configuration. Among these outputs, the output of the highest flip-flop is transferred to the first flip-flop as shown in FIG. 4c via an inverter 803.
The pulses are taken out as pulses S1 to S8 which send output over the range from channel time to eighth channel time.
Further, from the top flip-flop head pump, pulses S, -Sl6, which are inverted versions of the pulses S1-S8, are taken out as they are, as shown in FIG. 4d. Also,
The parallel 4-bit output signal outputted from the counter 801 is matched with the AND gate 804 to detect a full count state, and the output at this full count is taken out as a pulse Sl6 as shown in FIG. 4e, and By extracting this pulse Sl6 via an inverter 805, a pulse Sl6 is obtained as shown in FIG. 4f. In other words, this pulse Sl6 is generated every time (16 .mu.s) for one allocation processing operation in the channel processor 200, and requires time for each channel time to cycle twice. This is because the channel processor 200 compares the input key code KC with the stored key code KC, which has already been assigned, in the first 8 channel times, and then performs the writing process in the following 8 channel times. , and the pulses S, ~S8 and pulse S shown in FIGS. 4C and d mentioned above.
, ~Sl6 separates the first 8 channel time from the latter 8 channel time. Furthermore, the AND gate 806 determines the coincidence of the first to third outputs of the parallel 4-bit outputs output from the counter 801, and outputs the output at the 8th channel time as shown in FIG. 4R. Pulses S8 and Sl6 are obtained.
Pulses S8, S sent out from this AND gate 806
l6 is the clock pulse φ1 and the clock pulse φ1
The signal is supplied to an eight-stage shift register 802 which is shifted and driven by a two-phase clock pulse consisting of a clock pulse φ2 having an opposite phase to the clock pulse φ2, and is sequentially shifted up in synchronization with each channel time. As shown in FIG. 4 j-Q, pulses BTl to BT8 are obtained by sequentially sampling the first to eighth channel times. Therefore, the outputs of each stage of the shift register 802 are taken out in parallel of timing signals corresponding to the first to eighth channel times. Furthermore, the first to seventh stage outputs of the shift register 802 are
The clock pulse φA shown in FIG. 8h is obtained by determining the coincidence between the output of the OR gate 80r and the most significant bit output of the counter 801 at the AND gate 808.
Further, the AND gate 809 obtains the clock pulse φB shown in FIG. 8 by determining the coincidence between the output of the OR gate 807 and the output of the inverter 803. The trough operation is executed using such pulse signals and clock pulses as timing signals. Hereinafter, the operation of each part will be explained in detail for each block using the above-mentioned timing signals. Regarding the key coater 100, the patent application No. 50-99152, title of the invention "Key Coater" (Japanese Patent Publication No. 57-3948), which was previously filed by the applicant, and the title of the invention, Patent Application No. 50-100879. "Key switch detection processing device" (Japanese Patent Publication No. 57-3949) or Japanese Patent Application No. 51-75065, title of the invention "
Since it is explained in detail in the specification of "Electronic Musical Instrument" (Japanese Patent Publication No. 57-57719), the explanation thereof will be omitted here.

Channel Processor 200 First, the configuration and operation of channel processor 200 will be explained in detail.

5 to 8 are circuit diagrams showing specific embodiments of the first key code memory 201, key on/off detection circuit 202, truncate circuit 203, and key press state memory 204 that constitute the channel processor 200. . The first key code memory 201 shown in FIG.
Shift register 205a for each bit KN, ~KB, of
~205t, and this shift register 205a
The number of stages (number of storage positions) of ~205 fA corresponds to the number of musical tones that can be produced simultaneously, that is, the number of channels (in this embodiment, 8 channels as described above). The shift registers 205a to 205f are operated by the clock pulse φ1 shown in FIG.
, are driven by two-phase clock pulses consisting of clock pulses φ, which are opposite in phase to , and are sequentially shifted, and the output signal output from the final stage is output from the valley AND gates 206a to 206a.
206f and valley OR gates 207a to 207f to be fed back to each input side of each shift register 205a to 205t. Therefore, the shift registers 205a to 205t as a whole constitute an 8-stage circular shift register having a number of stages capable of storing key codes KC of parallel bit configuration for the number of channels. become. Further, on the input side of the valley shift registers 205a to 205V, a key code KC constituted by bits KNl to KB,
are supplied through each AND gate 208a-208t and each OR gate 20ra-20rr. Therefore, when a set signal is supplied to line 209 from a key-on/off detection circuit 202, which will be described later, each AND gate 208a to 208 opens, and each bit signal KNl to KB3 of key code KC is taken in, and each shift signal is input. register 2
All data is written and stored in stage portions corresponding to channels 05a to 205f to which key codes KC have not yet been assigned. Stored key code KC (
It can be determined to which channel the signals KN, -KB3) are assigned based on the output timing of each shift register 205a-205f driven by clock pulses .phi., .phi.2. This is because the clock pulses .phi., .phi.2 and the channels on which the time-division allocation process is performed are synchronized and correspond to each other. Therefore, the memory key code KC assigned to the valley channel
is shown in Figure 4b. "It is outputted to the output terminals 210a to 210f in a time-divisional manner for each channel time indicated, and is also fed back to the input side of each soft register 205a to 205f to continue holding the memory. Note that the OR gate 20rV has an initial value When the clear signal 1C is supplied, the Xll signal is forcibly written at that timing.Next, the key-on/off detection circuit 202 shown in FIG. Ori,
Memory key code KC output from each shift l register 205a to 205f of the first key code memory 201
and the key code KC currently supplied from the key code 100.

In this case, the stored key code KC corresponding to each channel supplied to the key code comparison circuit 211 is
It is designed to be supplied in circulation twice during one allocated time TP shown in FIG. In other words, each channel time from 1st to 8th goes through one cycle in the first half allocation period TP, (Fig. 4c), and once again in the second half allocation time TP2 (Fig. 4c).
2 because it circulates. On the other hand, key code 100
Since the key code KC output from the sample hold circuit 106 is read out by the clock pulse φB shown in FIG. 4, the contents of the key code KC do not change during one allocation period TP. Therefore, in a circuit configured in this way, one allocation period TP
By circulating the contents of each of the shift registers 205a to 205r twice and outputting them, it is possible to determine whether or not the key code KC currently being output from the key coater 100 has already been stored in the first half allocation period TPl.
A comparison operation is performed to see if it has already been assigned to a certain channel, and in the second half assignment period TP, an assignment operation is performed based on the first half comparison result. Further, the coincidence detection signal EQ output from the key code comparison circuit 211 is ^1 when a coincidence is obtained as a result of the comparison.
If n does not match, it is 601. In this comparison, whether the input key code KC matches the key code KC assigned to which channel is determined based on the channel time during which the match detection signal EQ becomes "1". Here, regarding the case where the input key code KC is not assigned to any channel and the match detection signal EQ of 10゛ is continuously output from the key code comparison circuit 211 during the first half assignment period TP. Considering this, when the coincidence detection signal EQ of "0" is output, the output signal of the AND gate 212 also becomes 0. and is stored in the delay flip-flop 215 via the AND gate 214. In this case, since one input terminal of the AND gate 214 is supplied with the pulse signal Sl6 shown in FIG. Memory contents (in this case, indicates that the input key code KC is not assigned to any channel...
0' signal) is held until the end of one allocation period TP. The output signal "O" of the delay flip-flop 215 is inverted by the inverter 216 and then supplied to the AND gate 217. A shift register 2 is driven in synchronization with each channel time by clock pulses φ1 and φ2.
18 is provided, and the allocation status of each channel is written in this shift register 218 as ``0'' for a blank channel and ``1'' for an assigned channel, and is sequentially shifted. Therefore, a blank channel is designated by determining the output of this shift register 218 and by the generation channel time of the "0" output. “O” indicating a blank channel from the shift register 218
When the ``output'' is generated, the ``00'' signal is output to the inverter 219.
The signal is supplied to the AND gate 217 via. in this case,
The other three input terminals of the AND gate 21r are supplied with the "1" signal supplied via the inverter 216, the pulses S, ~Sl6 (FIG. 4d) indicating the second half allocation period TP2, and the key code KC. Since the 81" signal is supplied from the OR gate 220 to detect that the channel is empty, the output of the AND gate 211 is becomes 1”2, and this f-th 2
” signal is supplied as a set signal to line 209 of the first key code memory 201. When this set signal is supplied, the first key code memory 201 associates the input key code KC with a blank channel as described above. In this case, the shift register 218 stores the stage corresponding to each channel in the first key code memory 201 in order to output a whisper 0 signal for every blank channel at its corresponding channel time. Same for all 7 stages corresponding to the back blank channel.
An input key code KC of 1 will be written. The AND gate 221 (FIG. 6) uses the gate input of the AND gate 21r and the truncate signal as gate inputs. As will be described later, this truncate signal is generated at the channel time corresponding to the oldest channel by determining the channel for which the key was released the earliest.
It is becoming more and more common for this phenomenon to occur. Therefore, from the AND gate 221, the set signal sent from the AND gate 217 corresponds to the channel for which the key was released earliest among the channels corresponding to each stage in which the input key code KC was written. A channel time signal is output. The 81'' output signal of this AND gate 221 is written to the shift register 218 via the OR gate 222.In other words, the oldest separated signal specified by the truncate signal among the channels to which the set signal is output from the AND gate 21T is written to the shift register 218 via the OR gate 222. The 11° signal is written to the storage stage of the shift register 218 corresponding to one keyed channel, indicating that the channel has already been assigned.In other words, a new input key code is written to the storage stage of the shift register 218. When KC is supplied from the key coater 100, if this new input key code KC has not yet been assigned to any channel, the shift register 21
A blank channel is specified by the output signal of 8, and a set signal is output from the AND gate 21T at a timing corresponding to the time of the specified blank channel. As a result, new input key codes KC are commonly written to the stages corresponding to all the blank channels specified by the shift register 218 among the stages corresponding to the valley channels of the first key code memory 201. be included. -On the other hand, a 1'' signal is written in the stage corresponding to the blank channel of the shift register 218, indicating that the channel has become an assigned channel only in the stage corresponding to the one channel for which the key was released the earliest. be included.

Next, a case where the input key code KC has already been stored in the first key code memory 201 and has been assigned to a certain channel will be described.

If the input key code KC has already been assigned to a certain channel, the coincidence detection signal EQ of the key code comparison circuit 211 becomes 61n during that channel time. This coincidence detection signal EQ=61 is applied to the AND gate 21
2. At this time, the output signal of the OR gate 220 is "1". Therefore, the coincidence detection signal EQ is "8".
199 and the output signal of the shift register 218 is ゛゛1.
” (that is, the channel time of the channel to which the input key code KC has already been assigned), the AND gate 212 holds the condition and outputs 6P.
A signal is output. This indulgence 1 signal is OR gate 213
and is supplied to the delay flip-flop 215 via the AND gate 214, and held until the end of one allocation period TP (FIG. 4), as in the case described above. However, an inverter 216 is provided on the output side of this delay flip-flop 215, and when the match detection signal EQ=619 is output from the key code comparison circuit 211, the AND gate 21T and the AND gate 221 to 81'' Since no signal can be obtained, the assignment operation is not executed.The above operation is the channel assignment operation of the input key code KC in the key-on/off detection circuit 202.

Next, the key release detection operation of the key-on/off detection circuit 202 will be explained. In the channel assignment operation described above, the AND gate 221 outputs a "1" signal at the channel time corresponding to the channel for which the assignment has been executed, and the assignment of this channel to the stage corresponding to that channel of the shift register 218 is completed. Therefore, this soft register 218 stores the allocation status of each channel, and the information stored in this shift register 218 corresponds to the channel time. The clock pulses φ, , φ2 are sequentially shifted, and sequentially output from the final stage and supplied to the key press state memory 204, which will be described next. On the other hand, the signal indicating the assigned channel output from the AND gate 221 is output from the OR gate 22.
8 with the same configuration as the shift register 218
The data are sequentially written and stored in the stage shift register 225.

Therefore, at this point, the shift register 225
The contents of are the same as the contents of shift register 218, and are sequentially shifted by the same clock pulses φ, , φ,. The signal output from the final stage of the shift register 225 is returned to its input side via the AND gate 226 and held there. Next, the sample hold circuit 10 of the key coater 100 shown in FIG.
6 to 4, which is set every time all of the operation key switches are converted to the corresponding key code KC and sent out.
In the state state (standby state), the clock pulse φB
The start signal X sent out at the timing of is supplied to the AND gate 226 via the inverter 22r, inhibits the AND gate 226, and thereby all the stored contents of the shift register 225 are reset.

After this reset operation is completed, the shift register 225
is the output signal of AND gate 221 and AND gate 2
The output signal of AND gate 212 is written through 28. By performing such an operation, the X1 signal is written in the shift register 225 to the stage corresponding to the channel to which the key switch being operated after the fourth state (waiting state) is assigned. Self-holding until the next start signal X is generated. On the other hand, since the shift register 218 does not perform any resetting operation, the 611 signal continues to be stored in the corresponding stage even for channels whose keys are subsequently released.

In this case, when the fourth state is entered again and the start signal X is supplied, the output signal of the shift register 225 is no longer fed back to the input side, but is supplied to the NAND gate 230 via the inverter 229. This NAND gate 230 receives pulse signals S1 to S8 shown in FIG.
, start signal X1, the inverted output signal of the shift register 225, and the output signal of the shift register 218 are supplied.

Therefore, in the fourth state and the pulse signal S, ~
The outputs of the shift register 218 and the shift register 225 are compared only during the period S8 (the first half allocation period TP). Then, when the output of the shift register 218 is 81'' and the output of the shift register 225 is 07, that is, after the latest fourth state, the key code K assigned to that channel is
If the same key code KC as C is not continuously supplied (that is, the key has been released), the output of the inverter 229 becomes ``17'', so the output of the NAND gate 230 becomes ``O'' and the key code is released. Detect channels in key state. Therefore, by determining the channel time of the 80'' signal output from this NAND gate 230, it can be determined which channel the key was released on.The 8'' output signal of this NAND gate 230 is
of shift register 218 to inhibit
r'' output signal is no longer returned to the input side, and as a result, the 11'' signal of the stage corresponding to the channel that has already been released is forcibly rewritten to the 10'' signal. The 61" signal indicating the allocated state is changed to the "O" signal indicating the blank channel state. Note that 231 is the 40" signal indicating that the key release channel output from the NAND gate 230 has been detected.
This is an inverter that supplies a "1" signal, which is an inverted signal, to a truncate circuit 203, which will be described next.

Next, the truncate circuit 203 will be explained. FIG. 7 shows a specific embodiment of the truncate circuit 203. When a channel in which a key is released is detected by the NAND gate 230 of the key-on/off detection circuit 202 described above, this key-release channel detection signal is Inverter 23
1, it is inverted to a 1 bit signal and stored in a delay flip-flop 235 via an OR gate 234. The output signal of this delay flip-flop 235 is AND gate 2
36 and the OR gate 234, it is returned to the input side and held. In this case, since the other input of the AND gate 236 is supplied with the pulse signal Sl6 shown in FIG. 4f, the contents of the delay flip-flop 235 are held until the end of the allocation period TP and then reset. Ru. In this state, when an output is sent from the shift register 218 of the key-on/off detection circuit 202, a "'1" signal is supplied from the inverter 237 during the blank channel time corresponding to the unassigned channel. , in the second half allocation period TP2 (pulses S9 to Sl
6) from the AND gate 238 to the shift register 2
In response to the 80" output of 18, a pulse signal of 11." is sent out.As will be explained later, the NAND gate 239
The output of is "P" in this case. This and gate 23
The output signal of 8 is supplied to the input terminal CI of the adder 240, whereby "1" is added to the 3-bit augend signal supplied to the input terminals A1 to A3, and this addition result is added to the 3-bit augend signal. The signals are outputted from the output terminals S1 to S3. In this case, the output terminals S1 to S3 of the adder 240 are connected to AND gates 241a to 241c, each of which uses the output of the inverter 237 as one input signal, and only when the 6P'' signal is output from the inverter 237. , that is, the AND gate 241a is executed only when the channel time corresponds to a blank channel that has not been allocated.
241c are opened, and the 3-bit addition result signal is supplied to the input terminals of shift registers 245a to 245c via OR gate 242 and AND gates 243 and 244, respectively. In addition, ANDGATE 24
3,244 is supplied via an inverter 246'
"1・" signal (in this case, initial clear signal 1C
has not occurred). The shift registers 245a to 245c are constructed of shift registers having storage stages corresponding to the number of channels (8 stages in this embodiment), and their input signals are sequentially input by clock pulses φ1 and φ2 synchronized with the channel time. It is shifted and sent out from the final stage. Each output signal of the shift registers 245a to 245c is transmitted to each input terminal A1 to A3 for the augend signal of the adder 240 described above.
are supplied respectively. Therefore, each time the key-on/off detection circuit 202 detects the above-mentioned key release, the current state is detected in the stage corresponding to the blank channel of the shift register 218 among the stages of each shift register 245a to 245c. 1 to count value sequentially
This constitutes a key release channel progress storage circuit 247 that adds up. This key release channel progress storage circuit 247 has a shift register 24 with an 8-stage configuration.
Since 5a to 245c are used in a three-stage parallel configuration, the parallel 3-bit key release progress signal given to each channel is sequentially shifted in accordance with the channel time, and the oldest key release signal is shifted sequentially corresponding to the channel time. The key release progress signal having the largest value at the channel time corresponding to the keyed channel is output as a 3-bit signal (binary code). In this case, since the key release channel progress memory circuit 247 has a 3-bit configuration as described above, its maximum output value is 7 (811P), and when 1 is added to this, it becomes 0.
C'000'), and the oldest key-released channel becomes the most recently released channel. For this purpose, on the output side of each shift register 245a to 245c, there is a NAND gate 239 for matching 3-bit signals.
is provided, and by inhibiting AND gate 238 with the output signal of NAND gate 239, subsequent additions are stopped in that channel, thereby eliminating the above-mentioned disadvantage. By performing the above-described operation, the circuit to be described later can sequentially perform the assignment operation starting from the channel with the oldest key release. This is because sustain is added after a key is released, so if many keys have been operated, it is necessary to determine the oldest key release channel and assign a new key code. Key release channel progress memory circuit 2
The 3-bit key release progress signal output from 47 corresponding to each channel time is passed through an AND gate 248 for each bit.
a-248c and OR gates 249a-249c to delay flip-flops 250a-250c for storage. In this case, since the 3-bit signal stored in each delay flip-flop 250a to 250c is read in with clock pulse φ1 and read out with clock pulse φ2, it will be delayed by one clock pulse and output. Each of these output signals is returned to the input side via each AND gate 251a to 251c and each OR gate 249a to 249c, and the memory thereof is held. Therefore, delay flip-flops 250a-250c constitute a storage circuit for storing 3-bit signals. The output signals of delay flip-flops 250a-250c are 3
The signal is supplied to the comparator 252 as a bit key release progress signal B. The comparator 252 compares the key release progress signal B with a new key release progress signal A that is removed from the key release channel progress storage circuit 247, and generates a [P' output only when A>B. It is composed of The output signal from the comparator 252 is supplied to each AND gate 251a to 251c as a competitive signal via a NOR gate 253, so that it is applied to each delay flip-flop 250a to 250.
Prevents the output of c from returning to the input side. Furthermore, since the 6P" signal output from the comparator 252 is supplied to the AND gate 254, the AND condition is satisfied at the output timing of the comparator 252 in the first half allocation period TPl, and the The output causes each bit signal of the new key release progress signal A from storage circuit 247 to be stored in delay flip-flops 250a-250c via AND gates 248a-248c.
Therefore, these are the maximum key release progress signal extraction circuit 25 that extracts the maximum key release progress signal of each channel.
At the end of the first half allocation period TPl, only the maximum key release elapsed signal is stored in the delay flip-flops 250a to 250c, and the pulse signal Sl6(
It is reset at the end of one allocation period TP according to FIG. 4e). Further, the output signal of the AND gate 254 generated in the first half allocation period TPl is supplied to each AND gate 256a to 256c, and in this timing, the output signal of the AND gate 254 is outputted from the counter 801 of the timing signal generating section 300 shown in FIG. A signal that encodes each channel of bits, that is, a channel code signal HC.
l to HC3 (binary coded channel times) are stored in each delay flip-flop 258a to 258c via each OR gate 257a to 257c, respectively. And this delay flip-flop 258a~
The contents of 258c are the maximum key release elapsed signal extraction circuit 25.
5, since the output signal of the NOR gate 253 is supplied to the AND gates 259a to 259c, the channel code signals HCl to H representing the channel in which the maximum key release elapsed signal occurs within the first half allocation period TPl are
C3 will be stored. A channel code signal HC representing the channel in which the maximum key release elapsed signal stored in each of the delay flip-flops 258a to 258c occurred.
1 to HC3 are held until the end of one allocation period TP (FIG. 4). It is set by the pulse signal Sl6 (FIG. 4e) supplied via the NOR gate 253. Further, the channel code signals HCl to HC3 stored in the delay flip-flops 258a to 258c are as follows.
The human channel code signal H is supplied to the comparator 260.
A match between Cl and HC3 is sought. When the two signals match, a match signal of 1 is outputted at that timing and sent to the AND gate 221 of the key-on/off detection circuit 202 as a truncate signal. In this case, channel code signals HCl to HC3 are applied during one allocation period TP (fourth
In order to cycle twice during the period shown in FIG. 1, writing to each of the delay flip-flops 258a to 258c is performed during the first cycle period (first half allocation period TPl), so the coincidence output signal at the comparator 260 is It will be output only once in a certain channel time in the second half allocation period TP2. Therefore, these circuits constitute the oldest key release channel extraction circuit 261, and in the second half of the allocation period TP2, the oldest key release channel (the channel in which truncation is most progressing) is extracted. A pulse signal as a truncate signal is output at the corresponding channel time, and the channel to which a new key code KC is to be assigned is reliably specified to the key-on/off detection circuit 202 only once. Note that in the key release channel progress storage circuit 247, writing the initial clear signal IC only to the shift register 245a via the OR gate 242 is done by first writing the 1P' signal to all stages of the shift register 245a, and then writing the 1P'' signal to all stages of the shift register 245a. This is to ensure the truncation operation. That is, the shift registers 218 and 225 of the key-on-off detection circuit 202 are reset in the initial state when the power is turned on by an initial clear signal 1C (not shown). Along with this, the output signal of the NAND gate 230 is always ``1'' at first, and therefore the output signal of the delay flip-flop 235 is also 80'', and the AND condition of the AND gate 238 is no longer satisfied. When all of ~245c are also reset, the comparator 252 in the maximum key release elapsed signal extraction circuit 255 outputs 1 when A>B.
...It becomes impossible to get a signal. As a result, channel code signals HCl to H
C3 is no longer stored and each delay flip-flop 25
8a to 258c continue in the state set by the pulse signal Sl6 supplied via the NOR gate 253. As a result, the condition AB is not obtained in the comparator 260, the truncate signal is not generated, and the first generated key code KC is not assigned. In order to solve this problem, the 61' signal is forcibly written to all stages of the shift register 245a using the initial clear signal 1C. Therefore, the writing of the "1" signal by this initial clear signal 1C is not necessarily limited to the shift register 245a, but the 711 signal is forcibly written to at least one of the three-stage shift registers 245a to 245c. It is sufficient if the configuration is as follows.

The above description is the operation of the truncation circuit 203 that specifies only one channel that has been truncated the most. Next, the key press state memory 204 will be explained in detail.

FIG. 8 shows a specific embodiment of the key press state memory 204, in which output signals from the shift register 218 of the key-on/off detection circuit 202 described above are sequentially supplied to each AND gate 262a to 262h. ing.

As described above, in this shift register 218, the 61 signal is written only in the stage corresponding to the channel to which the key code KC is assigned, and the stage corresponding to the key-released channel (blank channel) has been rewritten as 60n. Therefore, the signals sent from the shift register 218 in a time-division manner corresponding to each channel time represent the current key depression state of the key assigned to each channel. This state is memorized and the Kurotsuta pulse φ
When the output signal of the shift register 218 sent out while being sequentially shifted by 1 and φ2 is introduced into the key press state memory 204, the output signal is in the straight 0 state, that is, the key corresponding to the assigned key code KC is During the channel time during which the key is pressed, the timing signal generator 800 shown in FIG. 3 outputs signals for each channel (corresponding to the channel time) in a time-divisional manner as shown in FIG. 4 1-Q. The conditions of the AND gates 262a to 262h where the timings of the channel signals BTl to BT8 match are satisfied, and the output of the carp 1'' is applied to the OR gates 263a to 263.
Delay flip-flops 264a-264h through 3h
and its output is stored in AND gates 265a to 265.
h and is returned to the input side via OR gates 263a to 263h, thereby being held. Therefore, the delay flip-flops 264a to 264 in charge of the first to eighth channels are activated by the ""1" signal indicating the key depression channel provided from the shift register 218 (FIG. 6).
The competitive signal is stored only in the portion in charge of the corresponding channel of h, and the next corresponding channel signal BT, ~BT8, which is generated in a time-division manner, inhibits the AND gates 265a-265h via the inverters 266a-266h. It will continue to be held until For example, at the third channel time shown in FIG.
(Fig. 6), when the 1° signal is output, this third
The channel signal generated during the channel time is shown in Figure 4.1.
As shown in , there is only channel signal BT3. As a result, the condition is satisfied only in the AND gate 262c,
The output signal is written to delay flip-flop 264c via OR gate 263c. Therefore, these circuit portions delay the output signal of the shift register 218 (FIG. 6), which indicates the key depression state of each channel, by the channel signals BTl to BT8 to the flip-flops 264a to 264a.
By sequentially writing to 64h, a serial-to-parallel conversion circuit 267 is configured that converts the signal representing the key press channel from the shift register 218, which is serially output in a time-division manner, into eight channels of parallel signals.

From this serial/parallel conversion circuit 267, output lines 268a to 268 corresponding to each channel are connected.
Among h, the "P' signal is output only to the channel to which the key code KC is assigned and the key corresponding to the key code KC is pressed. For example, as described above, the "P' signal is output to the third channel. If the key is pressed, the 111 signal is output to the line 268c.In this way, the shadow 1 signal output corresponding to the key pressed channel is
The first to eighth
Output terminals 271a-2 provided corresponding to the channels
The 'f1.9 signal is sent at 71h. For example, as mentioned above, if only the third channel is pressed,
The Suga1'' signal is supplied from the delay flip-flop 264c to the NOR gate 269c via the line 268c, and only the transistor 270c is turned off by this NOR gate 269c(7) Suga0n output signal.As a result, only the output terminal 271c is turned off. 17, and the other output terminal 271a
, 271b, 271d to 271h are 60''. Therefore, among these output terminals 271a to 271h,
11 indicates that a key is being pressed in the corresponding channel. And this 61″
The signal, that is, the key-on signal KO, is sent to a corresponding tone pitch voltage control circuit 5 of a channel-by-channel tone pitch voltage control section 500, which will be described later.
01a to 501h are controlled. Key Code Conversion Unit 300 Next, the key code conversion unit 300 will be explained in detail.

FIG. 9 shows a specific embodiment of the key code converter 300 shown in FIG. 1, in which a key code shift control terminal 301 controls the presence or absence of pitch variable control (clissand effect or voltament effect). This is a terminal for inputting a pitch variable control signal for the purpose of the present invention, and when obtaining a normal musical tone, a 3-bit signal is supplied, and when performing pitch variable control, a 607 signal is supplied. It's summery.

The signal introduced to the key code shift control terminal 301 is applied to the addition/subtraction circuit 338 of the arithmetic circuit 303 to control its operation. Manual terminals A1 to A of the addition/subtraction circuit 338
Each bit KNl-KB3 of the key code KC output from the first key code memory 201 (FIG. 5) of the channel processor 200 is manually input to the input terminals B1 to B7.
Each bit KNl' to KB3' of the key code KC' outputted from the second key code memory 302 is input to B7, and each bit KNl' of the key code KC' outputted from the output terminals S1 to S7 is inputted to B7. ~KB3' are supplied to the second key code memory 302.

Here, the second key code memory 302 is constituted by seven shift registers 313a to 313g, each having eight storage stages equal to the number of channels and sequentially shifted by clock pulses φ1 and φ2. As in the case of the first key code memory 201 described above, key codes KC' having a 7-bit structure are stored for the number of channels and are sequentially shifted. When the 61'' signal is supplied to the key code shift control terminal 301, the addition/subtraction circuit 338 outputs the key code KC from the first key code memory 201 inputted to the input terminals A1 to A7 as it is without making any changes. The key code Kσ is outputted from the terminals S1 to S7, and when the 109 signal is supplied to the terminal 301, the key code KC inputted manually to the input terminals A1 to A7 is blocked, and the second key code Kσ is inputted to the input terminals B1 to B7. A signal input manually to the addition control input terminal (G) or subtraction control input terminal (D) is added or subtracted to the key code KC7 from the key code memory 302, and the result of the calculation is output to the output terminals S1 to S.
Output from 7.

As a result, when glitsando performance or portamento performance is selected (when the ``''0n signal is supplied to the terminal 301), the second key code memory 302 is The key code KC' output from the key code memory 302 changes sequentially.The key code KC' output from the second key code memory 302 is supplied to the sampling circuit 401 of the key code pitch voltage conversion section 400. The pitch change direction determination circuit 304 is based on the third key code memory 31.
4, a fourth comparator 315, a demultiplex circuit 316, flip-flops 317a to 317g, and a multiflex circuit 318.

First key code memory 2 of channel processor 200
The key code KC output from 01 is sent to the fourth comparator 315.
is supplied to the a input side of the key code memory 314 as well as to the third key code memory 314. The third key code memory 314 is composed of seven shift registers 315a to 315g, each having eight storage stages equal to the number of channels and sequentially shifted by clock pulses φ1 and φ2. The key code KC of each channel sequentially outputted from the 1-key code memory 201 is delayed by 8 channel times (hereinafter referred to as 1 cycle) in which each channel time completes one cycle, and is outputted and supplied to the c input side of the comparator 315. The comparator 315 compares the key code KC currently output from the first key code memory 201 supplied to the a input side.
C is output from the first key code memory 201 by comparing, at each channel time, the key code KC related to the same channel that was output from the first key code memory 201 one cycle before being supplied to the human power side. It detects for each channel whether the key code KC has changed to the treble side or the bass side, and if the key code KC has changed to the treble side (a>c
If the key code KC changes to the bass side (if a<c), a 6P'' down signal D is sent out.

Note that when the key code KC has not changed (a=c), the signals U and D are not sent out. In this way, the up signal U1 down signal D for each channel, which is sequentially sent out from the comparator 315, is
The input terminals A and B of the demultiplex circuit 316 are respectively driven in synchronization with Tl to BT8 (FIG. 4 j to Q).

The demultiplex circuit 316 distributes and supplies the up signal U or down signal D as a pitch change direction discrimination signal output from the fourth comparator 315 for each channel to flip-flops 317a to 317g provided for each channel. In response to the up signal U or down signal D, the flip-flops 317a to 317g are stored as set or reset states. The information on the direction of pitch change (rising or falling) stored in the flip-flops 317a to 317g for each channel continues to be stored until the direction of pitch change in that channel becomes the opposite direction. This flip-flop 317a~
The stored information of 317g, that is, the set output signal Q, is taken out in a time-divisional manner corresponding to each channel time by a multi-flex circuit 318 which is driven in synchronization with each channel time BT1 to BT8. Therefore, the signal W sent out from the multi-flex circuit 313 represents the pitch change direction of each channel. This signal W is supplied to the arithmetic circuit 303 and controls the operation of the arithmetic circuit 303. Furthermore, the preset switch 305 outputs a digital value K for setting the amount of overshoot in glitsando or voltamento performance. Supplied.

The first key code memory 201 is manually operated by the adder 306.
The adder 306 adds the digital value K output from the preset switch 305 to the key code KC, thereby creating a glysand whose pitch changes in an upward direction. The first comparator 308 outputs the key code KC+K indicating the upper limit of the key code change when performing (portamento) performance.
d input. Further, the a input of the subtracter 307 is supplied with the key code KC output from the first key code memory 201, and the subtracter 307 extracts the digital key code K output from the preset switch 305 from this key code KC. Key code KC-K that indicates the lower limit value of key code change when performing a gris sando (portamento) performance in which the pitch changes in a downward direction by subtraction.
is output and supplied to the e-manpower of the second comparator 309. 1st
The key code KC' output from the second key code memory 302 is provided to the f inputs of the comparator 308 and the second comparator 309, respectively. When the key code KC' output from the key code KC' reaches the upper limit key code KC+K or the lower limit key code KC-K, a d1' signal is output. Furthermore, the third comparator 310 detects the end of a key code change in a gris sando (portamento) performance, and its a and f inputs have the key code KC and the second key code output from the first key code memory 201, respectively. The key code KC' output from the key code memory 302 is disconnected, and the comparator 31
0: When the key code KC' matches the key code KC, a 1'' signal is output. Each comparator 308, 30 mentioned above
The comparison output signal output from 9,310 is sent to the arithmetic circuit 30.
3 to control the arithmetic operation of the arithmetic circuit 303. Note that the addition operation of the adder 306, the subtraction operation of the subtracter 307, and the comparison operations of the comparators 308, 309, and 310 are performed independently and time-divisionally for each channel in synchronization with each channel time. . Arithmetic circuit 30
3, eight flip-flops 327a to 327f and 324a to 324a are provided corresponding to each channel.
3247 stores the state of the key chord change (pitch change) in the glitsando (portamemento) performance of the corresponding channel, and the flip-flops 327a to 3277 store the key chord change (pitch change) state from the start of the key chord change (start of the glitsando performance). The "1" signal is stored until the code change reaches the upper limit value (KC+K) or the lower limit value (KC-K) of the overshoot, while the flip-flops 324a to 3247 store the "1" signal until the key code change reaches the upper limit value (KC-K).
+K) or the lower limit (KC-K), and the repeat signal is stored until the end of the key code change (end of the glissando performance).

The set input terminals S of the flip-flops 327a to 327t receive signals obtained by differentiating the key-on signals KOl to KO8 of each channel outputted from the key press state memory 204 (FIG. 8) by rise differentiation circuits 328a to 328t, respectively. As a result, the flip-flops 327a to 327t are assigned a new operation key to sound in their respective corresponding channels, and when the key-on signals KOl to KO8 change from ``゜0゛ to 61゛ (that is, the key code starts changing). When the flip-flops 327a to 3277 are set, the second key code memory 30 is set as will be described later.
The process of sequentially increasing or decreasing the key code KC' of the channel output from 2 is started, but this sequentially changing key code KC' is the overshoot upper limit value key output from the adder 306. code KC
+K or when the overshoot lower limit key code KC-K output from the subtracter 307 is reached, the comparator 308 or 309 outputs a "1" signal at the channel time as described above. vessel 308
, 309 is supplied to input terminal A of the demultiplex circuit 319 via an AND gate 320 or 322 and an OR gate 323. Demultiplex circuit 31
Reference numeral 9 is driven by channel signals BTl to BT8 (j-Q in Figure 4), and the time-division signals supplied to input terminals A and B in synchronization with each channel time are sent to output terminals for each channel. Output is distributed to A1 to A8 and B1 to B8 respectively.These output terminals A1 to A8
The output signals of rising edge differentiating circuits 326a to 326 respectively
7 to the set input terminals R of the flip-flops 327a-327f, and also to the set input terminals S of the flip-flops 324a-3247. Further, the output signals of the output terminals B1 to B8 are connected to the flip-flops 324a to 324y and the set input terminal R, respectively.
is supplied to Therefore, as described above, comparator 308
Or, when a 1゛ signal is output from 309 in a certain channel time (when the change in key code KC' reaches the overshoot upper limit key code KC+K or lower limit key code KC-K), the corresponding channel of the demultiplex circuit 319 An 11' signal is sent from the output terminals A1-A8 corresponding to the channel, thereby setting the flip-flops 327a-327t corresponding to the channel and also setting the flip-flops 324a-324t. As a result, the key code KC' of the channel output from the second key code memory 302 is changed from the overshoot upper limit key code KC+K or lower limit key code KC-K to the first key code which is the final value of the key code change.
Processing is performed to sequentially change the key code KC of the new operation key of the channel output from the key code memory 201. And the second key code memory 3
When the key code KC' output from the AND gate 3 reaches the final value of the key code change, a "1" signal is output from the third comparator 310 at the corresponding channel time, and the AND gate 3
40 to input terminal B of the demultiplex circuit 319. As a result, the flip-flops 324a to 324t corresponding to the channel are set, the change in the key code KC' of the channel output from the second key code memory 302 is stopped, and the glissando (portamento) performance is completed. Each flip-flop 327
The set output signals Q of a to 327t and 324a to 324y are respectively synchronized with timing signals BTl to BT8 (fourth
Multiflex circuit 32 driven by Figures j-Q
9 and 325 and taken out corresponding to each channel time.

The output signals of the multiflex circuits 329 and 325 are output to AND gates 331, 332 and 334, respectively.
, 335. ANDGATE 331 and 33
The output signal W of the pitch change direction discrimination circuit 304 and the arithmetic control pulse 0PC output from the synchronous differentiation circuit 330 are supplied to other inputs of AND gates 332 and 335. A signal obtained by inverting the output signal W of the force direction determination circuit 304 by inverters 333 and 336, respectively, and an arithmetic control pulse 0PC are supplied.
Here, the synchronous differentiator circuit 330 performs an operation in which a speed control pulse TC with an extremely long period is supplied to the speed control terminal 312 from a pitch voltage control section 700, which will be described later, and has a pulse width of 8 channels from the rise of the speed control pulse TC. Generate control pulse 0PC. This is so that each channel key code KC' outputted from the second key code memory 302 can be subjected to one calculation process each time the speed control TC is supplied. Therefore, and gate 331
and 335 indicate the calculation control pulse 0 in the channel time of the channel in which the key code KC' output from the second key code memory 302 is to be changed sequentially in the order of high notes.
Outputs 11” signal every time PC occurs, and OR gate 3
37 to the addition control input terminal (G) of the addition/subtraction circuit 338.
supply to. On the other hand, the AND gates 332 and 334 output the ``1'' signal every time the arithmetic control pulse 0PC is generated during the channel time of the channel in which the key code KC' output from the second key code memory 302 is to be sequentially changed to the bass side. It is outputted and supplied to the subtraction control input terminal of the addition/subtraction circuit 338 via the OR gate 339. When the addition/subtraction circuit 338 receives the "1" signal at the addition control input terminal (G), the addition/subtraction circuit 338 outputs the input terminals B1 to ? the second being supplied to
Add "1" or "2" to the key code KC' from the key code memory 302, output the addition result from the output terminals S1 to S7, and input it to the rare subtraction control input terminal (to).
When the 1'' signal is supplied, "1" or "2" is subtracted from the key code KC' supplied to the input terminals B1 to B7, and the subtraction result is outputted from the output terminals S1 to S7.

The key code FK output from the second key code memory 302 by the addition or subtraction operation of the addition/subtraction circuit 338
C' changes to the treble side or the bass side. In this case, addition (subtraction) of "1" is performed in the addition/subtraction circuit 338.
The output signal of the code detector 311 indicates whether to perform the addition (subtraction) of "2" or the addition (subtraction) of "2". When the output signal of the code detector 311 is "1", " addition (subtraction) is instructed, and when "01", "2
" addition (subtraction) is instructed. By the way, the note code NC constituting the key code KC uses a binary code with ≠ note C as a reference and a semitone as one unit, as shown in Table 1.

In other words, when expressed in decimal ◆, note C is "O", note D is "1", fathom note D is "2", note E is "4",
Note ≠ F is "5", Note F is "6", Note G is ≠ "8", Note G is "9", Note A is "10", ◆
Note A is assigned as a binary code "12", note B as "13", and note C as "14".

That is, the note code NC is not set so that the difference between the note codes of each note name directly corresponds to the pitch between those note names. In this case, the note code NC is composed of 4-bit signals KNl to KN4, and
゛While it can take 16 different values up to 111 bits,
This is because there are 12 tones in one octave. As is clear from Table 1 above, here bit KNl
and KN2 are both "1"° 1001
“゛,ゞ゛0111″,゛101F゛,゛1111゛ are not used, and the remaining 12 codes are C-
It is assigned to the 12 notes of C.

As a result, if a semitone is taken as one unit, the difference in note chords is
There will be locations 1 and 2. As is clear from Table 1, the block code BC has a continuous chord structure in units of one octave.

Therefore, when changing the key code KC sequentially by semitones, there will be a part where "1" (in decimal notation) is added or subtracted from the key code KC, and a part where "2" (in decimal notation) is added or subtracted from the key code KC. .

Specifically, looking at the case where the key code KC is raised and lowered at semitone intervals, the note code of the current key code KC + ◆ ≠ the note NC is C, D, E
, F, G, G, A, or B, add 0 to "1"; to represent any of the pitch names D≠, F≠, A, or C, use "2". , to create a key code KC of a tone a semitone higher.

In this case, the lower two bits KN2 and KNl of the note code NC for each note of CD, E, F, G, GA◆, and B are ゛00
'' or 10F', so when this is detected, it is sufficient to add "1", and at other times, it is sufficient to add "2".

Similarly, if we consider the case where the key code KC is sequentially "descended" at semitone intervals, the current note code NC is D,
To represent any of the pitch names D≠, F, F fathom, G◆, A, B, C, subtract “1” and write C◆, E, G, A
To represent any of the note names in ◆, subtract "2" to create a key code KC of a note a semitone lower.

In this case as well), the lower two bits KN2 and KNl of the note code NC of each note of DpD≠PF9F≠TG≠'AFLC are "0F" or "10", so when this is detected, subtract "1". ``2'' otherwise.
It would be a good idea to perform the subtraction of . In this way, in order to create a key code KC that ascends (descends) sequentially at semitone intervals, determine the lower two bits KN2 and KNl of the current note code NC and add "1" to the current key code KC. (subtraction) or addition (subtraction) of "2".

Therefore, the key code converter 300 shown in FIG. 9 is provided with a code detector 311 for determining the lower two bits KN2 and KNl of the note code NC.

That is, the output KNl' of the shift register 313a of the second key code memory 302, the output KN2' of the shift register 313b, and the output signal W of the pitch change direction determination circuit 304 are input to the code detector 311. When the key code KC/ is raised by a semitone (signal W is ``1''), the code detector 311 detects that KN2' and KNl' are 600'' or 10 Bi, and outputs a 1r'' signal. "
In other cases, an O' signal is output to instruct addition of "2". In addition, the code detector 31
1 is for lowering the key code KC' by a semitone (signal W
is '0''), KN2', KNl' is '01' or 6
It detects that it is 10゛, outputs the ``1'' signal, and outputs the ``1'' signal.
”, and otherwise outputs a 0 signal to instruct subtraction of “2”. Thereby, the key code KC' output from the second key code memory 302 can be raised or lowered sequentially at semitone intervals. Next, the operation of the key code converter 300 will be specifically explained.
First, when performing a normal performance, a "1" signal is supplied to the key code shift control terminal 301. Addition/subtraction circuit 3
38, when a "1" signal is supplied to the key code shift control terminal 301, the first key code memory 20 of the channel processor 200 is input to the input terminals A1 to A7 as described above.
The key code KC supplied from 1 is sent directly to the output terminal S1.
~ S7 is supplied to the second key code memory 302. Therefore, during normal operation when the "1" signal is supplied to the key code shift terminal 301, the key code KC of each channel supplied from the first key code memory 201 in a time-division manner is sent to the adder/subtracter circuit 338 and The signals are sequentially output as key codes 1KC' via the second key code memory 302 and supplied to the key code tone pitch voltage converter 400. This results in a normal performance musical tone. Next, key code shift control terminal 3
A case will be described in which a "0" signal is supplied to 01 and the key code KC is converted.

Note that this key code conversion unit 300 performs the key code conversion process for each channel in a time-sharing manner at the corresponding channel time, but in order to make the explanation easier to understand, the operation for one channel will be explained below as a representative. do. to the key code shift control terminal 301”
When the 0° signal is supplied, the addition/subtraction circuit 338 blocks the key code KC from the first key code memory 201 that is supplied to the input terminals A1 to A7, and also blocks the key code KC from the first key code memory 201 that is supplied to the input terminals A1 to A7.
The stored state is continued by returning the key code KC' from the second key code memory 302 supplied to B7 to the second key code memory 302 via the output terminal Sl-S7. In this state, when a new key is operated and the sound is assigned to a channel (in the following explanation, it will be referred to as the first channel) with this operation key (second operation key),
The key code KC output from the first key code memory 201 in synchronization with the first channel time is the previous operation key (first
The key code KCl corresponding to the second operating key changes from the key code KCl corresponding to the second operating key to the key code KC2 corresponding to the second operating key. Due to a change in the key code KC output from the first key code memory 201 during the first channel time, the up signal U or the down signal D is output from the fourth comparator 315 in the pitch change direction determining circuit 304 as described above. It is output in synchronization with the first channel time. As a result, the flip-flop 311a corresponding to the first channel is set or reset. This flip-flop 317a
The set output signal Q is taken out in synchronization with the first channel time in the multiflex circuit 318, and is sent to the arithmetic circuit 303 as a pitch change direction determination signal W representing the direction of pitch change (upward or downward) in the first channel. Supplied. For example, if the pitch of the second operating key is higher than the pitch of the first operating key, the pitch change direction determination signal W of the first channel becomes "W1".On the other hand, the channel processor 200
As a result, the key-on signal KOl of the first channel outputted from the key press state memory 204 in response to the assignment of the second operation key to the first channel is 10? Rising from “61”,
As a result, the flip-flop 327a corresponding to the first channel is set. This flip-flop 32
The set output signal Q (6F" signal) of 7a is taken out in synchronization with the first channel time in the multiflex circuit 329 and supplied to the 8-AND gates 331 and 332. At this time, as described above, the pitch change direction discriminating circuit 3
Since the pitch change direction discrimination signal W for the first channel is output from 04, either the AND gate 331 or 332 becomes operable depending on whether the discrimination signal W is ``1'' or 0. A signal "1" is output from either the AND gate 331 or 332 in the first channel time at the timing when the calculation control pulse 0PC is generated.For example, if the pitch of the second operating key is higher than the pitch of the first operating key. If the pitch change direction of the first channel is rising and the pitch change direction discrimination signal W is ``1'', the AND gate 3
31 outputs the ``1'' signal during the first channel time,
This “11 signal” is supplied to the addition control input terminal (G) of the addition/subtraction circuit 338 via the OR gates 33 and 7. As a result, in the addition/subtraction circuit 338, the 1 channel key code KC' (initially the key code KC of the 1st operation key
"1" or "2" designated by the code detector 311 is added to the key code KC' which is a semitone higher than the key code KC', which is then stored in the second key code memory 3.
02, and the memory 3 is input at the next first channel time.
Output from 02. And again the calculation control pulse 0PC
When this occurs, the AND gate 331 outputs the ``1'' signal during the first channel time and supplies it to the addition control input terminal (G) of the addition/subtraction circuit 338. "1" or "2" is added again to the key code KC' of the 1st channel, and it is further converted into a key code KC' that is a semitone higher. In this way, each time the calculation control pulse 0PC is generated (terminal 312
(Every time the speed control pulse TC is supplied to)
Since "1" or "2" is calculated in the key code KC' of the first channel output from the second key code memory 302, the key code KC of the first channel output from the second key code memory 302 ' is set to the initial value of the key code KCl of the first operating key, and gradually changes upward at semitone intervals as shown in FIG. 10a. In addition, when the pitch change direction of the first channel is in the downward direction (the second operation key pitch is lower than the first operation key pitch) and the pitch change direction discrimination signal W is ``0'', the calculation control pulse 0PC 11 from the AND gate 332 at the first channel time each time
'5 signal is output This "1" signal is OR gate 33
9 to the subtraction control input terminal of the addition/subtraction circuit 338. As a result, each time the arithmetic control pulse 0PC is generated, the key code KC' of the first channel output from the second key code memory 302 is changed to "1" or "2".
" is subtracted, so the key code KC of the first channel
' is the key code K of the first operation key as shown in Figure 10b.
With Cl as the initial value, it changes downward sequentially at semitone intervals. In this way, the key code C' of the first channel output from the second key code memory 302 changes sequentially upward or downward from the original key code KCl of the first operation key, but this sequential change key code KC
' is supplied to comparators 308 and 309. In this case, the adder 306 and the subtracter 307 output a preset value to the key code KCl of the first channel output from the first key code memory 201, that is, the key code KC2 of the second operating key, in the first channel time. switch 3
Upper limit value key code KC2+ that is added or subtracted from the digital value K that determines the amount of overshoot set in 05.
K or lower limit key code KC2-K is output, respectively, and upper limit key code KC2+K and lower limit key code KC2-K are input to comparators 308 and 309, respectively. As a result, the key code K of the first channel output from the second key code memory 302
C' increases or decreases sequentially to reach the upper limit key code K.
When it matches C2+K or the lower limit key code KC2-K, a 1" signal is output from the comparator 308 or 309 in the first channel time and is supplied to the AND gates 320 and 322, respectively. In this case, the pitch change If the direction discrimination signal W is "1" and the sequential change of the key code KC' is in the rising direction, the AND gate 320 is enabled and the key code KC' is the upper limit value key code KC2.
The ``1'' signal output from the comparator 308 when the voltage reaches +K is supplied to the input terminal A of the demultiplex circuit 319 via the AND gate 320 and the OR gate 323.
On the other hand, the pitch change direction discrimination signal W is "0" and the key is 1K.
If the sequential change in C' is in the downward direction, the AND gate 32
2 is enabled to operate by the output of the inverter 321, so the key code KC' is the lower limit key code KC2-K.
The “1” signal output from the comparator 309 when First
When the key code KC' of the channel is increasing, the upper limit key code KC2+K for the first channel is set.
When the key code KC' is changing downward, the lower limit key code KC for the first channel is reached.
When it reaches 2-K, a 61" signal is sent from the output terminal A1 corresponding to the first channel of the demultiplex circuit 319. This causes the flip-flop 327a to be set and the set output signal Q to be changed from "1" to 3"0". At the same time, the flip-flop 324a is set and its set output signal Q rises from "0" to "11" (FIG. 10d). The set output signal Q (61'' signal) of the flip-flop 324a is sent to the multiflex circuit 3.
At 25, the signal is taken out in synchronization with the first channel time and supplied to AND gates 334 and 335. In this case, if the pitch change direction discrimination signal W is 011 and the pitch change direction is rising, a 1゛ signal is output in the first channel time every time the calculation control pulse 0PC is generated from the AND gate 334. The "1" signal is supplied to the subtraction control input terminal (d) of the addition/subtraction circuit 338 via the OR gate 339. As a result, the key code KC' of the first channel output from the second key code memory 302 becomes the 10th key code KC'.
As shown in FIG. a, after reaching the upper limit key code KC2+K, it begins to change downward at semitone intervals. On the other hand, if the pitch change force direction discrimination signal W is 'O' and the pitch change force direction is falling, a "1" signal is output in the first channel time every time the calculation control pulse 0PC is generated from the AND gate 335. The “1°” signal is supplied to the addition control input terminal (G) of the addition/subtraction circuit 338 via the OR gate 337. As a result, the key code KC7 of the first channel output from the second key code memory 302 is As shown in FIG. 10b, after reaching the lower limit key code KC2-K, it begins to change upward at semitone intervals.In this state, the first channel output from the second key code memory 302 When the key code KC' matches the key code KCl of the first channel outputted from the first key code memory 201, that is, the key code KC2 of the second operating key, the comparator 310 outputs "1" at the first channel time.
A signal is output.

At this time, since the output of the multiflex circuit 329 is O'', the AND gate 340 is enabled to operate by the output of the inverter 341, and the comparator 310 is
The "17" signal output is supplied to the input terminal B of the demultiplex circuit 319. As a result, the "1" signal is output from the output terminal B1 corresponding to the first channel of the demultiplex circuit 319, and the flip-flop 324a is set. The set output signal Q falls to "O" (FIG. 10d). As a result, the “1” signal is not supplied to the addition control input terminal (G) and the subtraction control input terminal (G) of the addition/subtraction circuit 338 during the first channel time, so that the “1” signal is not output from the second key code memory 302. The addition or subtraction operation to the key code KC' of the first channel is stopped, and the sequential change of the key code KC' is stopped.Therefore, from now on, the first key code KC' output from the second key code memory The key code KC' of the channel becomes the key code KC2 of the second operation key, and this state is maintained.This state is maintained after the second operation key assigned to the first channel is released and the assignment is cancelled. A new operation key is again assigned to sound in this first channel, and the pressed key state memory 20
The key-on signal KOl of the first channel output from 4
It continues until it rises to ゛1゛゜. In addition, the key code KC'
While changing from the upper limit key code KC2+K to the lower limit key code KC2-K, the key codes KC2 and KC
There is a point where ′ coincide, but at this time the output of the multiflex circuit 329 is 1′, so the inverter 3
The AND gate 340 is inoperable due to the output of 41, and even if the ``1'' signal is output from the comparator 310, it will not be supplied to the input terminal B of the demultiplex circuit 319.

In this way, when a new second operation key is assigned to sound in the first channel, the key code KC' of the first channel output from the second key code memory 302 is the key code of the previous first operation key. Upper limit value key code KC2+K (or lower limit value key code KC2-K) on the treble side (or bass side) from the code KCl to the key code KC2 of the second operation key
), and when the key code KC' reaches the upper limit key code KC2+K (or the lower limit key code KC2-K), the key code KC2 of the second operation key changes. It begins to change downward (or upward) towards .

As a result, a key code KC7 that changes with an overshoot characteristic is obtained as shown in FIG. . In the above explanation, only the first channel was explained, but the same applies to the other channels, and in each channel, the key code KC of the previously assigned key (key code KC of the first operation key) )
A key code KC' that changes with an overshoot characteristic from the key code KC of the newly assigned key (the key code KC2 of the second operating key) is formed. The above description is a detailed explanation of the structure and operation of the key code conversion section 300 that performs key code conversion when obtaining a portamento sound effect or a glitsando sound effect having overshoot characteristics, and this part is an explanation of the operation of the key code conversion section 300 that performs key code conversion when obtaining a portamento sound effect or a glitsando sound effect having overshoot characteristics. This is the most important part.

Key code/pitch voltage converter 400 Next, the key code/pitch voltage converter 400 will be explained in detail.

11 and 12 show a specific embodiment of the key code/pitch voltage converter 400, and this key code/pitch voltage converter 400 is constructed using the sampling control circuit 402 shown in FIG. , a sampling circuit 401 and a digital-to-analog conversion circuit 403 shown in FIG. In this case, in the key code/pitch voltage conversion section 400, the sampling control circuit 402 that generates the reference timing signal and control signal will be explained first. FIG. 11 shows a specific circuit diagram of the sampling control circuit 402.
The AND gate 404 receives a channel signal BT output from the timing signal generating section 300 shown in FIG.
8 and an initial clear signal 1C are supplied.
This initial clear signal 1C becomes "1" only once immediately after the power is turned on, and its pulse width (period of "1") corresponds to the times of the first to eighth channels. Therefore, the timing signal BT8 is output from the AND gate 404 only once immediately after the power is turned on. The output signal (timing signal BT8) of this AND gate 404 is inputted via an OR gate 406 to an eight-stage shift register 405 driven by clock pulses φ1 and φ2, and is sequentially shifted by clock pulses φ1 and φ2. Therefore, each stage of this shift register 405 outputs a signal (“1” signal) that is sequentially delayed from the timing signal BT8 output from the AND gate 404.
is output in synchronization with the first channel time to the eighth channel time. The first shift register 405
When one "1" signal written in the stage is shifted to the final stage, the output of the NOR gate 407a becomes "1".
Then, ``1'' is written again in the first stage.
Therefore, from now on, the shift register 405 receives the 011 signal output from the NOR gate 407a and sequentially shifts it. As a result, the shift register 405 operates in synchronization with the shift register 802 shown in FIG.
The same channel signal BTl-BT8 (FIG. 13 b-1 is output) as the channel signal BTl-BT8 outputted from 02. In this way, two channels are required to obtain the same channel signal BTl-BT8. shift register 40
The reason why synchronous driving is performed using 5,802 is that when a circuit is divided into multiple blocks and integrated, or when both are installed in a relatively distant part, it is not possible to use a single synchronous signal line. This is to easily obtain eight synchronized channel signals BTl to BT8 by using only one channel. The output signal of AND gate 404 is also supplied via OR gate 410 to the input side of a nine-stage shift register 411 driven by clock pulses φ1 and φ2. Therefore, from the final stage of this shift register 411, a signal ('1'' signal) obtained by delaying the timing signal BT8 output from the AND gate 404 by 9 channel times is output.
is output in synchronization with the first channel time. At this time, the first stage output to the eighth stage output of the shift register 411 become "O", so the "1" signal is output from the OR gate 407b which receives these as input, and this "F" signal is sent to the OR gate 410. is written to the first stage of the shift register 411 through the 11'' input from the NOR gate 407b.
The signals are sequentially shifted and output from the final stage after 9 channel times. That is, shift register 411
At first, the timing signal BT8, which is outputted only once from the AND gate 404, is input and sequentially shifted.
After that, it is renormalized and output from the Noah gate 407b ゛1
゛Input a signal and shift it sequentially. As a result, from the final stage of the shift register 411, the
As shown in , every 9th count (every 9th channel time) of clock panores φ1 and φ2, 11 pulse signals S
C will be output. Further, an inverted signal SC of the pulse signal SC shown in FIG. 13k is taken out from the inverter 412. Furthermore, the output signals of the first stage and the final stage of the shift register 411 are sent to the NOR gate 413.
As shown in FIG. 13n, a pulse signal SOF which becomes "O" only at the output of the 9th and 1st stages is outputted. The above is the explanation of the sampling control circuit 402,
The various pulse signals outputted here are used in the sampling circuit 401, which will be explained next, so that part will be explained in detail. FIG. 12 shows a specific embodiment of the sampling circuit 401 and the digital/analog conversion circuit 403, and shows the output key code K of the second key code memory 302 shown in FIG.
C' is controlled by each bit signal K by the pulse signal SC (FIG. 13j) supplied from the sampling control circuit 402.
Nl' to KB3' are the AND gates 414a to 4147
The signals are supplied to delay flip-flops 416a to 416t via OR gates 415a to 415y and stored therein.

The next pulse signal SC is supplied to the inverter 417, and the "0" output of the inverter 417 causes this stored information (memory key code) to be stored in each AND gate 418.
It is held until a~4187 is inhibited. In this case, since the shift register 411 in FIG. 11 has a nine-stage configuration, which is one stage more than the number of channels, as described above, the pulse signal SC output from the shift register 411 is generated for one cycle of the channel time. The pulse signal is synchronized with a different channel time each time. Therefore, the pulse signal SC, which is the final stage output signal of this shift register 411, causes the second key code memory 3 to
By sampling the output key code KC' of 02, key codes KC' of different channel times can be sequentially sampled. That is, as shown in FIG. 13j, the pulse signal SCl is the first channel signal B.
The key code KC' corresponding to Tl can be sampled and stored in the delay flip-flops 416a to 416V, and the pulse signal SC generated in the next cycle can be
2, the key code KC' corresponding to the second channel time BT2 is sampled and the delay flip-flop 416
a to 416t. Therefore, the sampling in this part is to decelerate the output key code KC' of the second key code memory 302 to 1/8 and sample it sequentially for each channel, and this sampled key code KC2 The stored state continues to be held until the next sampling. The reason for performing such deceleration sampling is that the digital-to-analog conversion circuit 403, which will be explained next, cannot follow high-speed operation, and the subsequent circuit system performs parallel processing divided by channel, so time-division processing is not performed. This is because it does not require the high speed performance of the key coater 100, channel processor 200, etc. that are currently used. Therefore, these parts are decelerated and the key code K for each channel is
This constitutes a sampling circuit 401 that sequentially takes in C'. Next, the key code KC2 decelerated and sampled by the pulse signal SC of the sampling circuit 401 and stored in the delay flip-flops 416a to 416t is divided into note codes KNl7 to KN42 and block codes KBl2 to KB32, respectively. The signals are supplied to decoders 419 and 420, where they are converted into parallel decimal signals, and a "1" signal is output only to the output terminal corresponding to the code.

For example, the key code KC representing the B note of the 5th block.
2 is supplied, "1011'5" is supplied to the input terminals A-D of the decoder 419, and "101" is supplied to the input terminals A-C of the decoder 420. Therefore, the block code Decoder 42 that converts KBl2 to KB3″
0, the 6F signal is output only to the output terminal 5. Also, a decoder 4 that converts the note code KNl''-KN4''
19, the "1" signal is output only to the output terminal 13. As a result, the transistors 420a to 420 connected to the output terminals of each decoder 419 and 420, respectively,
Among the transistors t and 421a to 421f, only the transistor 420b and the transistor 421a connected to the terminal 13 and the terminal 15 to which the output 10 signal is output are turned on. As a result, the potential at point A of the first voltage dividing circuit 422 configured to divide the power supply + by the voltage dividing resistors r' to 16r' is connected to the plurality of resistors r and R through the transistor 421a which is in the on state. A second voltage dividing circuit 42 configured by
3 is supplied to point a. On the other hand, when the transistor 420b is turned on by the output of the decoder 419 as described above, the potential at point b is taken out and output. In this case, the potential at point a is the block code KBl2 to K
Since the output signal of the transistor 420b is the output of the first voltage dividing circuit 422 selected corresponding to the block code KB3'' and the note code KNl
2 to KN4'', and this becomes a tone pitch voltage KV that controls a voltage-controlled variable frequency oscillator, which will be described later.The key code KC' supplied from the key code converter 300 is decelerated and sampled and sent to the decoder. 419,
420, resulting in an output signal that is held for one period of deceleration sampling, as shown in FIG. 13, 1, n. In this case, when converting a digital signal to an analog sound pitch voltage of V, transistors 420a to 420t connected to the output sides of decoders 419 and 420,
Due to the capacitance in 421a to 421f, etc. and the stray capacitance in the circuit system, the rising part of the conversion output signal (sound pitch voltage K) rises in line with the number of CR points, so there is some distortion. However, this problem does not become a problem as it is processed at the time of assigning the sound pitch voltage K to each channel, which will be explained next. The pulse signal SC generated in the sampling control circuit 402 is applied to each AND gate 424a of the digital-to-analog conversion circuit 403.
~424h is also supplied.

The other input terminal of each AND gate 424a to 424h is connected to a channel signal B shown in FIG. 13b-1.
Since Tl to BT8 are supplied, the pulse signal SC
Only the AND gate 424 to which the channel signal synchronized with the generation timing of FIG.
h to delay flip-flops 426a-426h. Since the pulse signal SC supplied to the AND gates 424a to 424h is the final stage output signal of the shift register 411 (FIG. 11) which has counted one clock pulse more than the number of channels as described above, the channel signal BTl ~BT8 corresponds to channel signals sequentially shifted by one. Therefore, this pulse signal SC is equal to the channel signals BTl-B.
This means that T8 is decelerated to 1/8 and sampled, and this sampled channel signal BTl'~
One of the BT8's is a delay flip-flop 42.
Next pulse signal S stored in any of 6a to 426h
It continues to be held until AND gates 427a to 427h are inhibited by the output signal of inverter 417 when C is supplied. In this case, channel signals BTl to BT8
and the deceleration sampling of key code KC' are the same signal,
In other words, this is performed using a pulse signal SC, and the key code KC' supplied to the key code/pitch voltage conversion section 400 is supplied at the channel time corresponding to the channel to which the key code is assigned. It's becoming like that. As a result, the pitch voltage K obtained by converting the key code KC" sampled by the sampling circuit 401 into an analog signal is taken in by the pulse signal SC, and the "1" signal is stored and held in the delay flip-flops 426a to 426h. All you have to do is supply it to the existing channel. Therefore, this delay flip-flop 426a~
By turning on the transistors 428a to 428h connected to the output side with the output signal 426h, the tone pitch voltage KV is transferred to the target channel (assigned in the channel processor 200) via the output terminals 429a to 429h. The high-tone voltage KV can be supplied only to the channel in which the In this case, AND gates 430a to 430h are provided on the output side of each delay flip-flop 426a to 426h, and each gate 430a to 430h is connected to the first gate output from the NOR gate 413 of the sampling control circuit 402 shown in FIG.
It is controlled by the pulse signal SOF shown in Fig. 3h. Since this pulse signal SOF is a signal in which the output of the first stage and the output part of the final stage of the 9-stage shift register 411 are "0", it is set to "01" for two channel times from the generation of the pulse signal SC. It becomes a signal.
The pitch voltage KV output from this digital-to-analog conversion circuit 403 to each channel becomes a signal in which the first two channels are inhibited, as shown in FIG. Only the tone pitch voltage K that is in a stable state with the sometimes occurring rounded portion completely removed is sent out. The above explanation is for the second key code memory 3.
A sampling circuit 401 decelerates and samples the key code KC' supplied from 02 and sequentially captures it for each channel, and converts the sampled key code KC2 into a corresponding analog signal to generate a tone pitch voltage KV.
This is a detailed explanation of the digital-to-analog conversion circuit 403 that supplies this pitch voltage KV to the channel to which this key code KC2 is assigned.

Channel-specific tone high voltage control section 500, musical tone forming section 600
, pitch voltage control section 700 Next, channel-specific pitch voltage control section 500, musical tone forming section 600, and pitch voltage control section 7
00 will be explained.

FIG. 14 shows a specific embodiment of the channel-by-channel tone high voltage control section 500, the tone forming section 600, and the tone pitch voltage control section 700.
0 is a sound pitch voltage control circuit 501a to 50 for each channel.
01h. The tone pitch voltage control circuit 501a in charge of the first channel operates a transistor 502 whose gate input is the key-on signal KOl outputted from the output terminal 271a of the key press state memory 204 shown in FIG. It has a key-on signal K
It turns on when the ``1'' output of KOlC (a signal indicating that a key is pressed in this channel) is supplied.In this way, the key-on signal KOlC is applied to this first channel.
When the transistor 502 is supplied, the tone pitch voltage K corresponding to the key code KO'' assigned to this channel is supplied from the digital-to-analog conversion circuit 403 to the first channel as described above. When the transistor 502 is turned on by the inverted key-on signal KOl, a differentiating circuit composed of resistors 503, 504 and a capacitor 505 is provided on the emitter side of the transistor 502. 5
The differential output when 02 is on is taken out as a positive pulse via an inverter 506. This inverter 5
The output signal 06 turns on the transistor 507, and accordingly, the capacitor 508 is rapidly charged with the pitch voltage KV. Further, a series circuit of a resistor 509 with a medium resistance value and a transistor 510 and a series circuit of a resistor 511 with a large resistance value and a transistor 512 are connected in parallel between both ends of the transistor 507. By selectively turning on transistors 510 and 512 when they are off, the charging time constant of pitch voltage K to capacitor 508 is selected. Note that the NAND gate 513, AND gates 514, 515, and OR gate 516 are used when controlling the tone pitch voltage K1 charged in the capacitor 508 by the output signal of the tone pitch voltage control section 700, which will be explained in detail later. It is. The above explanation is the configuration of the tone pitch voltage control circuit 501a in charge of the first channel portion, and the tone pitch voltage control circuit 501 of the other channel portions.
b to 501h also have the same configuration. Next, the tone forming section 600 has tone forming circuits 601a to 601h provided for each channel.

When looking at the first channel portion of the musical tone forming circuits 601a to 601h, the tone pitch voltage control circuit 5
CO6O2 which receives the terminal potential KVl of the capacitor 508 that charges the tone pitch voltage K provided at 01a and oscillates a sound source signal of the corresponding frequency; VCF6O3 which controls this sound source signal to form a tone; A VCA 6O4 controls the nip probe, and these are controlled by nip probe generators EG6O5 to EG607 triggered by a key-on signal KO1. In addition,
This nip probe generator EG6O5~607 is
Needless to say, it is under the control of an adjustment polyurethane provided on an operation panel (not shown). The musical tone forming circuit 601a of the first channel configured as described above
The output signal (musical tone signal) is outputted to an output terminal 901 via a mixing resistor 900a. A musical tone is generated from a speaker connected to this output terminal 901, and a musical tone forming circuit commonly used is used. It has a similar configuration. Also. Tone formation circuit 601 in charge of other channels
A to 601h have the same configuration, and their output signals (musical tone signals) are outputted to an output terminal 901 via mixing resistors 900b to 900h. The above is the configuration of the musical tone forming section 600. Next, the pitch voltage control section 700 will be explained.

This pitch voltage control section 700 is a section that controls the speed of voltamento or glitsando, switches between voltamento and glissando, and controls whether or not the pitch of the musical tone signal changes during sustain. Reference numeral 701 denotes an oscillator OSC composed of a voltage-controlled variable frequency oscillator, which outputs a relatively long-cycle speed control pulse TO corresponding to the output voltage of the variable resistor 702.

The output voltage of the variable resistor 702 is determined by the comparators 703, 704,
705, and is compared with reference values Vrl-R3 in each comparator 703-705. The reference values Vrl to Vr3 are such that Vrl>Vr2>Vr3. The output signal of the comparator 703 is sent to the key code shift control terminal 30 shown in FIG. 9 as a pitch voltage variable control signal.
1. 706 is a switch for switching between portamento P and glissando G; 707 is a switch for switching between the presence or absence of pitch change (glitsando or portamento) of the musical tone signal in the sustain state; and 708 is an OR gate.

Hereinafter, the channel-by-channel tone high voltage control section 500, musical tone forming section 600, and tone pitch voltage control section 700 having the above-described configurations will be described.
The operation will be explained in detail.

First, the operation will be described when the switch 706 is switched to the portamento side (the state shown in the figure) and the switch 707 is switched to the side without sustain control (the state shown).

In this state, when the sliding piece of the variable resistor 702 is positioned closest to the ground side, a voltage lower than the reference value Vr3 is output, and the oscillator 701 sends out a long-cycle oscillation output corresponding to this low voltage. This long period oscillation output is supplied as a speed control pulse TC to a speed control terminal 305 shown in FIG. 9. Since the voltage supplied from the variable resistor 702 is a signal lower than the reference value R3, each comparator 703, 704, 705
All of the comparison outputs become "O". Since the output of the comparator 703 becomes "O", this 10" output is sent to the key code shift control terminal 301 shown in FIG. 9 as a pitch variable control signal. Supplied as. Therefore, the arithmetic circuit 30
3, as described above, in each channel, the above-described addition or subtraction processing is performed sequentially with the above-described overshoot characteristic until the key code KC corresponding to the first operation key matches the key code KC corresponding to the second operation key. Do the following. The calculation speed in this case is, as detailed in the above explanation, performed every time the speed control pulse TC output from the oscillator 701 is supplied, and in this case, the calculation speed is extremely slow. When such arithmetic processing is performed, the key code KC' of each channel outputted from the second key code memory 302 rises or falls in a stepwise manner as described above. Therefore, the key code KC' of each channel output from the second key code memory 302
is a key code K in which arithmetic processing is performed every time a speed control pulse TC with an extremely long period outputted from the oscillator 701 is supplied, and the pitch changes sequentially by semitones.
It will be converted to C' and output. The key code KC' that changes at a slow speed is sampled in the sampling circuit 401, and then converted into a corresponding pitch voltage in the digital-to-analog conversion circuit 403 to control the pitch voltage corresponding to the channel. It is supplied to circuits 501a to 501h. In the following description, the first channel will be described. First, by assigning the key code KC corresponding to the second operation key to the first channel in the channel processor 200, the key is turned on from the output terminal 271a (sheath 8) in charge of the first channel of the key press state memory 204. signal KOl
is supplied. This key-on signal KOl is a signal that becomes "1" when the key is turned on. This inverted signal KOl turns on the transistor 502, and when the transistor 502 is turned on, a differential pulse is generated at the connection point between the capacitor 505 and the resistor 504. This differential pulse is inverted in an inverter 506 to become a positive pulse, and this positive pulse is applied to the gate electrode of a field effect transistor 507 via an OR gate 516, turning on the transistor 507 momentarily. During the period when the transistor 507 is on, the transistor 507
The high tone voltage KV of the first channel supplied to the drain electrode of Because the key code KC of the key was stored, this pitch voltage K initially has a voltage value corresponding to the pitch of the first operating key.)
is charged in the capacitor 508 within this instant, and a musical tone signal corresponding to the terminal voltage KV', that is, corresponding to the first operation key is generated. Further, when a key-on signal KOl of 11'' is supplied from the terminal 271a of the key press state memory 204, the input of the NAND gate 513 becomes 11''10'', and its output becomes ``17''. This 61' signal is supplied to the transistor 512, and the transistor 512 is kept in the on state while the key-on signal KO1 is supplied. The above-mentioned transistor 507 is turned on only at the instant of key-on, and therefore only the transistor 512 remains on thereafter. Thereafter, the pitch changes stepwise at a slow cycle from a voltage value corresponding to the pitch of the first operation key supplied via the digital-to-analog conversion circuit 403 to a voltage value corresponding to the pitch of the second operation key. Voltage K is high resistance 5
The capacitor 508 is charged via 11. Therefore, the charging time constant in this case becomes extremely large, and the pitch voltage KV that changes stepwise becomes the pitch voltage KV' that changes continuously and is supplied to the musical tone forming circuit 601a. Thus, a portamento effect is obtained in which the pitch of the second operating key changes continuously and slowly after overshooting the pitch of the first operating key. In this case, when the second operation key is released, the key-on signal KOl changes from "1" to "0", and accordingly, the input of the NAND gate 513 changes to "1" and its output. Ga゛0
”.As a result, charging to the capacitor 508 is stopped at the same time as the key is released, and no portamento effect can be obtained in the sustain section.On the other hand, when the switch 7
When 07 is switched to the sustain control side (opposite to the illustration), the 00'' signal is supplied to the NAND gate 513, and the transistor 512 remains on even when the key is released when the inverted key-on signal KOl becomes 16. Continuing, a portamento effect can also be obtained for the sustain part.Next, slide the variable resistor 702 slightly upward to set it to a value larger than the reference value Vr3.
When a voltage of a smaller value is outputted, the cycle of the speed control pulse TC output from the oscillator 701 becomes faster, the calculation cycle becomes faster, and the change in the pitch voltage KV becomes faster.

On the other hand, since the variable resistor 702 outputs a voltage equal to or higher than the reference value Vr3, the output of the comparator 705 becomes "1". This 11' signal is supplied to the AND gate 515, and the condition of the AND gate 515 is satisfied by the "1" output of the NAND gate 513, which is always output during the supply period of the key-on signal KO1. The "1" output of the AND gate 515 turns on the transistor 510 and charges the capacitor 508 through the medium resistor 509 with the tone pitch voltage KV which changes at a relatively fast speed. The charged voltage KV' of the capacitor 508 is converted into a musical tone signal in a musical tone forming circuit 601a, and a musical tone having a portamento effect with an overshoot characteristic that changes continuously at a relatively fast speed is obtained from a speaker (not shown). In this case, the reason why the transistor 510 is selected and turned on so as to reduce the charging resistance value when the tone pitch voltage K changes quickly is because the tone pitch voltage K changes relatively quickly when the charging time constant is large. This is because they become unable to keep up with changes. Next, when the variable resistor 702 is slid to output an even higher voltage, the outputs of the comparators 704 and 705 both become "1".

The "1" output of this comparator 704 is supplied to the AND gate 514 via the OR gate 708, and the "1" output is determined to match the NAND gate "513" output when the key-on signal KOl is supplied. The transistor 507 is turned on via the OR gate 516. As a result, if the tone pitch voltage KV changes quickly, the tone pitch voltage KV is passed through the transistor 507 to the capacitor 507.
8 is directly charged to create a fast-changing, gritsand-like portamento effect. Next, when the output voltage of the variable resistor 702 is further increased, the oscillator 701 outputs an extremely fast speed control pulse TC.

However, when such a high voltage is output from the variable resistor 702, this voltage becomes higher than the reference value Vrl, and accordingly, the output of the comparator 703 changes from "0" to "1". In this case, the output signal of the comparator 703 is supplied to the key code shift control terminal 301 of the arithmetic circuit 303 shown in FIG. When the output voltage of the comparator 70 is controlled to be higher than the reference value Vrl, the comparator 70
The output signal No. 3 becomes 11'' and the operation of the arithmetic circuit 303 is stopped to control the normal operation. The above operation is the operation for obtaining a portamento effect having overshoot characteristics.

Next, the operation for obtaining a glissand effect having overshoot characteristics will be explained.

To obtain a glissand effect, switch 706 is turned in the opposite direction as shown to supply OR gate 708 with a ``1'' signal.

When a "1" signal is supplied to the OR gate 708, this 0F
The signal is constantly supplied to the AND gate 514. On the other hand, the output of the NAND gate 513, which is the other input of the AND gate 514, is a key-on signal KOl indicating that the key assigned to the first channel is pressed.
When the key-on signal K is supplied, it is always "1" as described above. Therefore, the AND gate 514 receives the key-on signal K.
When Ol is supplied, the condition is always satisfied and a 1゛ signal is obtained, and this "11 signal" is sent to the OR gate 516.
The transistor 507 is turned on via the . As a result, as long as the output of the variable resistor 702 is equal to or less than the reference value Vrl, any value, that is, the change in the pitch voltage KV, will be the reference value Vrl.
When changing at a speed lower than the speed determined by l, the capacitor 5 for charging the sound voltage is always
08, and this capacitor 50
8, v' is changed in a stepwise manner in response to the stepwise change in the pitch voltage KV. Therefore, the musical tone forming circuit 601a outputs a musical tone signal that has an overshoot characteristic and whose pitch changes in a stepwise manner. This allows you to automatically obtain musical tones that change in sequence. It goes without saying that when the output of the variable resistor 702 becomes equal to or higher than the reference value Vrl, the arithmetic processing of the arithmetic circuit 303 is stopped and normal operation resumes, as in the case of portamento described above. Furthermore, when the switch 707 is switched to sustain control (opposite to the illustration), the "O" signal is always supplied to the NAND gate 513, and during sustain, the "O" signal of this NAND gate 513 is
The output is supplied from switch 706 through OR gate 708. AND gate 514 by the ``1'' signal.
The condition is satisfied, and the transistor 507 outputs 1F.
Since it continues to be on, you will be able to get the crissand effect even during sustain. In addition, the variable resistor 702 as an output voltage regulator has both the functions of portamento or glitsando speed control and pitch variable control (gritsando or portamento) on/off control. This is an extremely effective method for reducing the number of errors and making it relatively easy to operate even for beginners. In this case, the reference value Vrl
Needless to say, it is necessary to set the voltage value to such a rapid change that portamento and grissando effects cannot be obtained. In the above embodiment, the reason why the "11 signal is forcibly written to each stage of the shift register 2057 of the first key code memory 201 of the channel processor 200 by the initial clear signal 1C is that the high voltage charging capacitor is connected in advance. This is to charge the pitch voltage to a certain pitch in preparation for the first key operation.In other words, when trying to obtain a portamento effect (glitsando effect) from the first key, the pitch corresponding to one of the keys This is to set a starting point to start.In the above-described embodiment, in the arithmetic processing to obtain a key code that changes stepwise, a semitone is set as "1" or "1" or Only the case where a key code that sequentially changes along the overshoot characteristic is obtained by adding or subtracting "2" has been explained.
This invention is not limited to this, but may be applied to cases in which the desired pitch is changed sequentially as one unit, or to only a part of the scale (for example, skipping the black key part or applying only to the middle part), etc. It goes without saying that similar effects can be obtained even if various changes are made.

In addition, in the embodiment, a case has been described in which a key code changed in a stepwise manner is converted into analog and supplied to a voltage-controlled variable frequency oscillator, but there is no need to be limited to this. A musical tone signal may be digitally selected using a key code signal to obtain a musical tone.

Further, in the embodiment, a key coater that encodes and extracts key information is used, but the key information may also be extracted by scanning a key switch. As explained above, the electronic musical instrument according to the present invention changes the pitch of the generated musical tone from the pitch corresponding to the first operation key to the pitch corresponding to the second operation key. It is constructed so that the pitch is raised or lowered by one step to a value that exceeds the pitch of the second operation key, and then returns to the pitch of the second operation key, which is not possible with conventional electronic musical instruments. This has an excellent effect in that a new portamento performance sound effect or glissando performance sound effect that cannot be obtained can be obtained.

[Brief explanation of the drawing]

FIG. 1 is an overall configuration diagram showing an embodiment of an electronic musical instrument according to the present invention, FIG. 2 is a diagram illustrating the representation diagram of logic elements used in this embodiment, and FIG. 3 is a diagram showing the timing signals shown in FIG. 1. A detailed circuit diagram showing an example of the generation section, FIG. 4 is a waveform diagram showing various timing pulses generated in the timing signal generation section shown in FIG. 3, and FIG. 5 is a diagram of the first key code memory shown in FIG. 1. 6 is a detailed circuit diagram showing an example of the key-on/on detection circuit shown in FIG. 1; FIG. 7 is a detailed circuit diagram showing an example of the truncate circuit shown in FIG. 1; 9 is a detailed circuit diagram showing an example of the key press state memory shown in FIG. 1, FIG. 9 is a detailed circuit diagram showing an example of the key code converter 300 shown in FIG.
The figure is a waveform diagram for explaining the operation of the key code converter 300 shown in FIG. 9, FIG. 11 is a detailed circuit diagram showing an example of the sampling control circuit shown in FIG. 1, and FIG. 12 is the same as shown in FIG. 1. A detailed circuit diagram showing an example of a sampling circuit and an analog-to-digital conversion circuit, FIG. 13 is a waveform diagram of each part to explain the operation of the sampling control circuit, sampling circuit, and analog-to-digital conversion circuit, and FIG. 14 is a diagram shown in FIG. FIG. 2 is a detailed circuit diagram showing an example of a channel-by-channel tone high voltage control section, a musical tone forming section, and a tone pitch voltage leg section shown in FIG. 100...Key coater, 200...Channel processor, 300...Key code converter, 302...Second key code memory 18 3
03... Arithmetic circuit, 304... Pitch change force direction discrimination circuit, 305... Preset switch, 306... Adder, 307... ...Subtractor, 308...First comparator, 309...
...Second comparator, 310...Third comparator, 31
1...Chord detector, 400...Key code tone high voltage converter, 500...Channel-specific tone high voltage control unit, 600...Music tone formation Part, 7
00... Sound pitch voltage control section, 800...
Timing signal generator.

Claims (1)

[Claims] 1 A pressed key detection means for detecting a pressed key on a keyboard section and outputting key information corresponding to the pitch of the key, and forming key information that changes sequentially based on the key information output from the pressed key detection means. a sequentially changing key information forming means for outputting, a musical tone forming means for forming a musical tone signal corresponding to a pitch represented by the key information according to the key information outputted from the sequentially changing key information forming means; the first key corresponding to the pitch of the first key.
The key information and the second key corresponding to the pitch of the second key pressed next.
pitch change direction determining means for comparing the second key information with key information to determine whether the second key information is on the treble side or the bass side with respect to the first key information; and adding a predetermined numerical value to the second key information. or setting means for setting upper limit key information or lower limit key information representing a pitch above or below the pitch represented by the second key information by the pitch corresponding to this numerical value by subtracting the pitch represented by the second key information, and the sequentially changing key information The forming means is configured to sequentially increase the pitch from the first key information to the upper limit key information and then sequentially decrease to the second key information when the discrimination output of the pitch change direction discriminator indicates a pitch change to the higher pitch side. and, when the discrimination output indicates a change in pitch toward the bass side, key information that sequentially changes downward from the first key information to the lower limit key information and then sequentially changes upward to the second key information. , thereby obtaining a glissando performance sound effect or a portamento performance sound effect.