JPS5937630B2 - Signal phase fluctuation correction device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an apparatus for correcting the phase of a signal accompanied by phase fluctuation, and particularly to an apparatus for correcting the phase fluctuation of a reproduced video signal of a video player.

In video players such as VTRs, horizontal fluctuations occur in the reproduced video due to phase fluctuations contained in the reproduced video signal.

Therefore, when playing back images with a television receiver, phase fluctuations can be corrected by speeding up the response of the horizontal AFC circuit system of the receiver, but the receiver is already in the hands of the user. It is extremely difficult to implement various countermeasures for machines due to the variety of models and service technology. Therefore, it has been considered to insert a phase fluctuation correction device 3 between a video player 1 and a television receiver 2 as shown in FIG. First, consider the characteristics that the correction device 3 should have. First, the amount of horizontal fluctuation of the video relative to the amount of phase fluctuation of the input video signal in the television receiver 2, that is, the horizontal fluctuation characteristics, is determined by the transfer characteristics of the horizontal AFC circuit system.

In Fig. 2, which shows the relationship between the phase fluctuation frequency and the amount of phase fluctuation, the horizontal fluctuation characteristic of the receiver has an increase characteristic of approximately 6 dB10 ct in the low range of phase fluctuation, as shown by the broken line a, and In the high range exceeding the cutoff frequency fr, it is approximately 1.

Therefore, there is room for improvement for phase fluctuation components with low phase fluctuation frequencies. Considering such horizontal fluctuation characteristics of a television receiver, it is not necessary for the phase fluctuation correction device to have good characteristics over a wide band, but it is sufficient that the characteristics are as shown by broken line b in FIG. 2.

That is, it has a characteristic complementary to the broken line a, and when characteristics a and b are combined, the broken line c in FIG. 2 is obtained. The amount of phase fluctuation D, which is the flat characteristic of the curved line c, indicates the limit value of improved characteristics in the receiver, the bending point of the broken line a is the cutoff frequency Fr of the horizontal AFC circuit system of the receiver, and the bending point of the broken line b is the phase. The cutoff frequency Fc of the fluctuation correction device and the shaded range indicate the amount of improvement in horizontal fluctuation of the receiver image. Next, looking at the relationship between time and phase fluctuation shown in Figure 3,
Regarding the phase fluctuation d of the input signal to the correction device in the reproduced video signal from the video player 1, the purpose can be fully achieved by correcting only the high-speed change component to obtain a smooth phase fluctuation curve f.

In other words, the correction amount of the phase correction device does not require the entire difference between the phase fluctuation d and the reference phase r, but only the difference e with respect to the smooth phase fluctuation f, which can be corrected by the conventional horizontal AFC circuit in the television receiver. It becomes possible to correct the phase to r.

FIG. 4 shows a basic configuration diagram of a phase fluctuation correction device having the phase correction characteristic shown by line b in FIG. 2.

The video reproduction signal input from the signal input terminal 4 and having phase fluctuation is given to the clock control memory 5 as a write signal 511, while the synchronization separator 6 obtains a synchronization signal 601 having the phase fluctuation of the input signal. The synchronous coupling controller 7 is driven by a write start signal 531, a read start signal 541, a write clock signal 551,
A respective signal of the read clock signal 561 is generated, and in the synchronization coupling controller 7, the start signal 53 is generated by the high speed component of the phase fluctuation contained in the synchronization signal 601.
1 and the frequency of the clock signal 551, the read signal 521 from the clock control memory 5 driven by these signals becomes a signal from which high-speed components of phase fluctuations have been removed, and the signal is output to the signal output terminal 8. It is possible to obtain a signal corrected to The clock control memory 5 is a capacitor analog memory or an A-D. D-A
Use addressable memory such as random access memory with converter. Conventional memories of this type require a large capacity, and the periodic coupling controller for controlling them becomes complex. SUMMARY OF THE INVENTION An object of the present invention is to provide a phase fluctuation correction device equipped with a synchronous coupling controller that operates stably with a circuit configuration that is simpler than conventional ones.

Embodiments of the present invention will be explained in detail below with reference to the drawings.

FIG. 5 is a block diagram showing one embodiment of the phase correction device according to the present invention.

The input video signal with phase fluctuation input to the signal input terminal 4 is input to the memory 5 as a write signal 511, and is also sent to the synchronization separator 6 where it is output as a synchronization signal 601 with phase fluctuation.
are separated.

The separated synchronization signal 601 is input to a synchronization coupling oscillator 73 to generate a phase error signal. Here, the synchronously coupled oscillator 7
3 is composed of a phase comparator 731, a time constant circuit 732, and a voltage controlled oscillator 733.
The oscillation output of
Obtain a phase error signal with respect to 01.

This phase error signal is transmitted to a time constant circuit 732 having integral characteristics.
to the voltage controlled oscillator to form a phase-coupled oscillation loop.

The phase error signal obtained from the synchronously coupled oscillator 73 has its gain adjusted by the control amount adjuster 74 and is applied to the clock coupled oscillator 75.

The clock coupled oscillator 75 includes a phase comparator 751, a time constant circuit 752, a voltage controlled oscillator 753, and a one-frequency n wave number divider 7.
54 and a signal adder 756.

The oscillation output of the voltage controlled oscillator 753 is divided into one cycle by the n wave number divider 7.
The frequency is divided by n by 54.

On the other hand, the oscillation output of the oscillator 763 of the read clock generator 76 (the frequency is approximately n times that of the synchronizing signal) is divided by n by a frequency divider 764 and applied to the phase comparator 751, as described above. A phase difference signal with the output n of one frequency divider 754 is obtained.

This phase difference signal is applied to a signal adder 756 via a time constant circuit 752 having integral characteristics, and is applied to a control amount adjuster 756.
4 and is added to the output of voltage controlled oscillator 7 as a control signal.
53 to form a phase-coupled oscillation loop.

The memory 5 receives the oscillator of the voltage controlled oscillator 753 as the write clock signal 551, the output of the frequency divider 754 as the write start signal 531, and the oscillation output of the oscillator 763 of the read clock generator 76 as the read clock signal 561. , and the outputs of the frequency divider 764 are provided as the read start signal n 541, respectively.

FIG. 6 is a diagram showing the phase correction characteristics of the above device.

The phase transfer characteristic 1 of the synchronously coupled oscillator 73 is determined by the time constant circuit 73.
By setting a large integration time constant of 2, it has a low cutoff frequency F3, and a drop characteristic of 6 dB/0 ct below F3.

Further, the phase transfer characteristic j of the clock coupled oscillator 75 is determined by the time constant circuit 752, and its time constant is determined by the time constant circuit 73.
By setting it slightly smaller than that of 2, it has a slightly higher cutoff frequency F2 (F2>F3), and 6 above F2.
It has a falling characteristic of dB/0ct. That is, the time constant circuit 7
32 and 752, the read clock signal or write clock signal is generated lagging the phase of the synchronization signal or read clock signal, respectively.

The phase correction region is the difference between characteristic 1 and characteristic j above F3, which is shaded in FIG.

A phase correction device that achieves this is obtained, and the horizontal fluctuation of the image is improved. That is, since the synchronous coupling oscillator 73 constitutes a phase coupling loop, as is well known, the voltage controlled oscillator 733 cannot follow the frequency component with high phase fluctuation of the input synchronous signal 601. Therefore, the phase comparator 731 outputs only a phase error signal corresponding to high-frequency phase fluctuations.

The synchronously coupled oscillator 75 is also connected to a read clock generator 76.
Since the phase coupling loop operates using the signal from the synchronous coupling oscillator 73 as a reference signal, relatively low frequency components of the phase error signal from the synchronous coupling oscillator 73, which is added to the error signal input, are processed by the control loop. The oscillation frequency of the voltage controlled oscillator 753 is changed in accordance with the error signal of the high frequency component. As a result, an oscillation output whose phase changes according to the high frequency component of the phase fluctuation of the signal applied to the terminal 4 is obtained, so by using this as a write clock signal, the high frequency component of the phase fluctuation can be corrected. You can get the signal. In this way, the synchronous coupling controller 7 that controls the memory 5 can be realized only by using two phase coupling loops, so the configuration is simple.

In the above example, when the memory 5 has a storage capacity sufficient to store video information within one horizontal period, the timing of the read start signal 541 is set to the write start signal 5.
31 is located in the middle, the dynamic +TH range of the phase fluctuation correction operation has a range from - to -.

In reality, such a wide correction range is not required, and the necessary correction range only needs to be equal to the amount of phase fluctuation that gives the maximum value of the phase fluctuation speed of the video player, and it does not matter how many DC drift components there are. Therefore, by shortening the repetition period of the write start signal 531 and read start signal 541, it is possible to reduce the storage capacity of the memory 5. As described above, the phase fluctuation correction device according to the present invention can achieve sufficient phase fluctuation correction using a synchronous coupling controller with a simpler configuration than the conventional one, and can overcome the large scale of the conventional phase fluctuation correction device. This solves the drawback of being too complex and expensive to be used in home video players.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the connection of the phase fluctuation correction device, Figure 2 is a diagram showing the horizontal fluctuation improvement characteristics of a television receiver, Figure 3 is a diagram showing the relationship between time and the amount of phase fluctuation, and Figure 4 is a diagram showing the relationship between time and the amount of phase fluctuation. FIG. 5 is a diagram showing the basic configuration of a conventional phase fluctuation correction device, FIG. 5 is a diagram showing the configuration of an embodiment of the present invention, and FIG. 6 is a diagram showing the phase fluctuation correction characteristics of FIG. 5... Analog memory, 6... Synchronous separator, 73... Synchronous coupling oscillator, 75...
. . . clock coupled oscillator, 76 . . . read clock generator, 551 . . . write clock signal,
561... Read clock signal.

Claims (1)

[Claims] 1 Using a memory whose write speed and read speed can be controlled independently by the write clock frequency and read clock frequency, a signal having a synchronization signal and phase fluctuation is temporarily stored in this memory, and the operation of reading this is repeated. A signal phase fluctuation correction device includes: means for separating a synchronization signal having phase fluctuation information from a signal having phase fluctuation; a first oscillation means for performing coupled oscillation with a delay in the phase of the synchronization signal; means for generating a phase difference signal between the output signal of the oscillation means 1 and the separated synchronization signal; means for generating a read clock signal having a frequency substantially an integral multiple of the synchronization signal; and a phase difference signal of the read clock signal. a second oscillation means that performs coupled oscillation with a delay in response to the second oscillation means; and means for controlling the phase of the output of the second oscillation means using the phase difference signal; A signal phase fluctuation correction device characterized by: