JPS5937833B2 - Page information display method in character display device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is used as a peripheral device for an information processing device, and is particularly equipped with a memory that can store display information for multiple screens divided into pages, and has a page mode function, scroll mode function, etc. The present invention relates to a page information display method suitable for use in a character display device having a functional configuration capable of recognizing and displaying information spanning pages, such as a page advance function.

In recent years, as information processing devices have been required to have more functions and higher processing efficiency, character display devices, which are peripheral devices for information processing devices, are also required to display multiple screens of information divided into pages, for example. is stored in memory, and when the characters of the last line of a certain page are entered in the final input area on the screen, the information of the next page is entered. There are various functions such as a so-called scroll mode function that displays information and enters new information in the sequential final input area to move up or down the display contents sequentially, a so-called page advance function that alternately calls and displays the contents of different page areas, etc. A device with complex functions is required.

In character display devices that have a functional configuration that displays information across pages on one screen, there is a function that allows the operator to recognize which page area the currently displayed information belongs to. Although this is necessary, conventionally there has been no effective and highly practical page information display recognition means for this purpose. This invention has been made in view of the above circumstances, and provides a character display device with a functional configuration that is equipped with a memory capable of storing display information for multiple screens divided into pages, and capable of recognizing and displaying information spanning pages. By simply adding a simple configuration, the number of pages corresponding to the displayed information can be reliably and easily recognized and displayed without storing the page number information in memory, thereby impairing the display function. It is an object of the present invention to provide a highly practical page information display method in a character display device that can clearly recognize the page corresponding to display information without causing any confusion. An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the circuit configuration of a display control portion in a character display device. In Figure 1, 1
1 is a clock generator, and a clock pulse CPO outputted from this clock generator 1 specifies dot positions for forming display characters. Further, the clock pulse CPO is sent to, for example, an octal dot counter 2 and counted. This dot counter 2 outputs a clock pulse CPl for each line scan for one character, and this clock pulse CPl is 80+
It is sent to an n-ary character counter 3 and counted. In this case, the CRT display section is designed to display 80 characters in one line, and a non-display area for n characters is provided at the left and right ends of the CRT display section. For this reason, the count base of the character counter 3 is set to 80+n base. The count contents of the character counter 3 are sent to the character display area designation circuit 4. This character display area specifying circuit 4 outputs a 611 signal (Hc) at a timing one character earlier than a predetermined character display area, and this signal is sent to AND circuits 13 and 14, and is delayed by one character. It is sent to an AND circuit 6 via a delay circuit 5 having a time. Therefore, the delay circuit 5 outputs a 1'' signal in the character display area of the CRT display section, that is, in the character display area (80 characters) in the center excluding the non-display area for n characters at the left and right ends. The output of the character counter 3 is sent to the CRT display section as a horizontal synchronization signal (H-SYNC) and also sent to a 12-decimal line counter for counting.
1, 12, character generator 18, etc., and also sent to the line display area designation circuit 8. This line display area specifying circuit 8 outputs a signal '11' when the contents of the line counter 7 are in the display line period, and this output signal is added to the AND circuit 6.
The line counter 7 outputs a clock pulse every time one line of scanning (including line spacing) is completed, and for example, 24+
The data is input to an n-ary row counter 9. In this case, the CRT display section is capable of displaying 24 lines, and a non-display area for n lines is provided at the upper and lower ends. For this reason, the count base of the row counter 9 is set to 24+n base,
Its output signal is C as a vertical synchronization signal (V-SYNC).
It is sent to the RT display section and also sent to the CPU as an interrupt signal (INT) indicating the end of one screen. Further, the contents of the row counter 9 are sent to the row display area designation circuit 10. This row display area specifying circuit 10 outputs an "r" signal when the contents of the row counter 9 are in the display row area, and the output signal is applied to the AND circuit 6. The decoder 11 inputs the count contents of the character counter 3 and line counter 7, and outputs a signal "11" each time one line of character display period ends, and this signal is a fault signal (HALT). In other words, the CPU executes the trace described later.
It is sent to the CPU as a signal to change the display control unit from occupied to occupied. The decoder 12 inputs the count contents of the line counter 6 and outputs an 81° signal during a predetermined non-display period when one display line ends. The output of the area specifying circuit 4 and the clock pulse (CP
l) is input to the AND circuit 13, and its output is further sent to the count input terminal of the address counter 15 which specifies the address of the data memory 16. After the address counter 15 sets the start address (ST-A) sent from the CPU to instruct which page and line from which one screen worth of data should start, the AND circuit 13 The clock pulse (CP
The address data output from the address counter 15 is sent to the data memory 12, and the decoder 101 of the page recognition display circuit 100, which is the gist of the present invention, performs a step-by-step operation in synchronization with the address counter 15.
sent to. Here, the data memory 16 has a storage capacity of, for example, two screens divided into pages, that is, a capacity of two pages (Pagel, Page2).
Read/read configured by AM and sent from CPU
The read/write mode is designated by the write finger + (R/W), and display data is written or read for each character by addressing the address counter 15. Display data is sent to a display data register 17 having a capacity of one line of display characters (80 characters).

This display data register 17 transfers data read out from the data memory 16 in units of one character to an AND circuit 14.
This AND circuit 14 is supplied with a signal (He) obtained from the character display area specifying circuit 4 and a clock pulse CP1 obtained from the dot counter 2. . One line of display character data (80 characters) output from the display data register 17 in character units is sequentially sent to the character generator 18 in character data units. This character generator 17 generates a dot matrix character signal corresponding to the character data output from the display data register 14, and it generates a character signal for each line based on the count contents of the line counter 6 during the display line period. Output a signal. Since the character signal output from the character generator 18 is parallel data, it is converted into serial data by a P-S (parallel-serial) conversion register 20. That is, this P-S conversion register 20 receives the clock pulse CP.
It simultaneously reads parallel input data in synchronization with clock pulse CPO and outputs stored data serially in synchronization with clock pulse CPO applied via AND circuit 19, and the output signal is sent to CRT as a video signal via OR circuit 21.
Sent to the display section. Further, the gate of the AND circuit 19 is controlled by the output of the AND circuit 6. On the other hand, in the decoder 101 of the page recognition display circuit 100, when the contents of the address counter 15 reach a specific character position in the first display line of each page area (Page, Page 2) of the data memory 16, It outputs page recognition signals Pl and P2 of level P1 and P2.
l, P2 are connected to flip-flop 1 via OR circuit 102.
The signal P2 is supplied to the set input (S) of flip-flop 1032.

Each of the flip-flops 1031 and 1032 has a set input terminal (self) for one line (for example, lines O to 8 for character display and lines 9 to 11 for maintaining character spacing between lines, 12 lines in total). The count value (L,) corresponding to a certain character spacing line (for example, line 9) is sent from the line counter 7 as a set signal (R9).

The set outputs of the flip-flops 1031 and 1032 are connected to respective AND circuits 1041 and 10, respectively.
Sent to 42. The AND circuits 1041 and 1042 have display position control for displaying dot marks corresponding to the number of pages as page recognition information in the non-character display area corresponding to the line position where the page of displayed character data is switched. A signal is provided. That is, here, the count value H26 of the character counter 3 indicating the position one character before the first display character position on the first row (first row) of the page (this is the signal Hc output from the character display area designation circuit 4) ) and a line signal L for specifying the dot display position. Further, the dot signal D2 and the brushing signal f for displaying dots in a pulling manner are supplied to the AND circuit 1041 as control signals, and the above signal H26
, LO, f and the dot signal D5 are supplied to an AND circuit 1042. The outputs of the AND circuits 1041 and 1049 are outputted to the OR circuits 105 and 2 as page recognition dot display information.
1 to the CRT display unit. Also, the above decoder 1
1 inputs the count contents of the character counter 3 and line counter 6 and outputs a "1" signal every time one line of character display period ends, and this signal is sent to the CPU as a fault signal (HALT). sent to.

When the CPU receives this signal (HALT), it temporarily suspends access to the data memory 12 until one line of data is transferred from the data memory 12 to the display data register 14, which will be described in detail later. . Furthermore, CPU
When the interrupt signal (INT) is received, it is recognized that one screen of data display has been completed, and control operations such as designation of the next start address (ST-A) are performed. Figure 2 shows an example of page recognition information using dot marks when the data memory is configured with n pages.One dot mark is placed in the character non-display area in the first row of the first page, and one dot mark is also shown in the second page. Two dot marks are displayed on the first line, and n dot marks are displayed on the first line of the n-th page.

In this way, a number of dot marks corresponding to the number of pages are displayed at the start position of each page. FIG. 3 shows the display state on a CRT. Character data read from the data memory 16 is recognized and displayed in the character display area D-C with n characters x M lines (for example, 80 characters x 24 lines) as one page. The page recognition display circuit 10 shown in FIG.
The page recognition dot display information obtained from 0 is displayed in a specific area, that is, the page recognition display area PA-C.

FIG. 4 is a diagram for explaining in detail the dot display position on the first page, and shows the first line (LO) and third dot in the area PA-C in the H26 period in the first row of the first page. (
D2) A dot mark is displayed at the position. Also, FIG. 5 shows the display period and data transfer period in the one-line display period (Vi), where the LO to L8 period is the character display period (CDT), and the Lll period is the next line display data transfer period (Vi). TT).

FIG. 6 is a timing chart showing the relationship between the clock pulse CP1 and the signal Hc indicating the character display area. The effect will be explained here.

To make the explanation easier, one screen displayed on the CRT display is 1919 with address 0 of RAMl6 as the starting address.
The case where character information for 80 characters/line x 24 lines up to the address, that is, one page, is displayed will be explained. First, C
The beam is sequentially scanned along each line in the horizontal direction from the top to the bottom on the RT screen, and at the timing of V1 when the last line of the non-character display area, that is, the line counter 9 has a value of "1", and The value of the line counter 7 is "11", that is, the start address specifies the address where the first character of the characters to be displayed from the CPU side is stored at the appropriate time during the timing of LlO (the first information is for each line). ST-A is set in the address counter 15, that is, in this case, the address counter is set to address 0. And when the timing of 1・Lll comes, CP
From the U side, a read designation command is supplied to the data memory 16, and the decoder 12 outputs the "11 signal, which is supplied to the AND circuit 13.
When the value of the character counter 3 becomes "26", the character display area designation circuit 4 outputs a signal H.
c is output and supplied to the AND circuit 13 and the AND circuit 14. Therefore, AND circuit 13 and AND circuit 1
Gate 4 will be opened. As a result, the address counter 15 is sequentially incremented by the clock pulse CPl outputted from the AND circuit 13, character data is sequentially read character by character from the data memory 16, and the display data register 17
supplied to On the other hand, character data read out from the data memory 16 character by character is input to the display data register 17 character by character in synchronization with the clock pulse CP outputted from the AND circuit 14. In this way, each time the address counter 15 advances by one step in synchronization with the clock pulse CP, information for one character is read out from the data memory 16 and written to the display data register. For example, if the content is 6
When it is time to read address 4, that is, a specific character position (65th character) in the 1st line of the 1st page area, the decoder 101 of the page recognition display circuit 100 outputs the 1st page recognition signal P. Flip-flop 103 is set. The AND circuit 13 that obtains the count signal of the address counter 15 outputs the clock pulse CPl when the Hc signal during the non-display line (line 11) period is no longer output, that is, when the count value of the character counter 3 reaches "106". The output of the address counter 15 is inhibited, whereby the address counter 15 receives 80 clock pulses CP during the output period of the Hc signal.
After counting to 0, the counting operation is temporarily stopped. On the other hand, the AND circuit 14 that controls the shift of the display data register 17 also prohibits the output of the clock pulse CPl since the signal Hc is no longer output, and as a result, the display data register 17 is shifted from one page read from the data memory 16. The shift operation is temporarily prohibited when data for one line, that is, 80 characters, is stored.

Thereafter, the character counter 3 further receives the clock pulse C.
The count operation continues in response to Pl, and when the final count value is reached, the value of the line counter 7 changes from [11] to "0" with the carry signal at that time, and the value of the line counter 7 changes from [11] to "0" with the carry signal of the line counter 7. The value of 9 is incremented by 1 to indicate the value of the next line, and this enters the display period of the next line, that is, the first line display period of the first page.Thus, in this first line display period. In this case, character counter 3
When the count content becomes "26" again and the signal Hc is output from the character display area specifying circuit 4, the signal H26 at this time, the LO signal indicating the first line, the D signal indicating the third dot, and the brushing signal are output. When the signal f etc. is supplied to the AND circuit 1041, the AND circuit 1041
11-level page recognition dot display information is output from the ``11'' level page recognition dot display information.
21 to the CRT display section. As a result, C
A dot mark indicating the first page is displayed on the RT at the position shown in FIG. On the other hand, when the first clock pulse CPl is output after the signal Hc is output from the character display area specifying circuit 4, the AND circuit 14
The clock pulse CP1 is again supplied to the display data register 17 via the display data register 17, whereby the data of the first character stored in the display data register 17 is supplied to the character generator 18 and resuscitated. When the character generator 18 receives this one character data, it first calculates the count contents of the line counter 7 [
0'' (LO), a dot signal in units of 8 dots of the first display line (RO) for character data is output. Furthermore, this dot signal in units of 8 dots is the clock pulse CP.
It is stored in the Tp-s conversion register 20 in synchronization with l. Then, a signal 6 indicating the character display period is output from the AND circuit 6.
When r is output, P is synchronized with clock pulse CPO.
-S conversion register 20 serially outputs dot signals one dot at a time, and outputs them via OR circuit 21 to CRT.
It is sent to the display unit as a video signal. With this, CR
On top of T is the first letter L on the first page and first line. Dots for lines are recognized and displayed. Then, when the dot counter 2 counts the clock pulse CPO by 8 and outputs the clock pulse CP, the character counter 3
is counted up by 1, and the display data register 17 is shift-controlled by the clock pulse CP1 at this time, and the data of the second character is transferred to the character generator 1.
It is sent to 8th and resuccessed. The character generator 18 receives this second character data and outputs an 8-dot signal of the first display line (LO) for the character data in the same manner as in the case of the first character described above.
Furthermore, as in the case of the first character described above, after being stored in the P-S conversion register 20, it is sent to the CRT display unit in serial mode, and the second character L on the first page and first line is stored. Dots for lines are recognized and displayed. In this way, one line of character data stored in the display data register 17 is sequentially sent to the character generator 18.
It is converted into a dot signal for the first line (LO), and C
It will be recognized and displayed on RT. Display data register 1
The contents of character counter 3 go through one cycle and the contents of character counter 3 become [1
06'', the character display area specifying circuit 4 no longer outputs the signal Hc, and as a result, the AND circuit 1
4 is closed and the shift operation of the display data register 17 is temporarily stopped. Then, the character counter 3 receives the clock pulse CPl and continues counting operation.
When the carry signal is output, the line counter 7 is incremented by one, and its content becomes "1". As a result, the character generator 18 is supplied with a signal (L1) indicating the second line instead of the signal (LO) indicating the first line. After that, the count content of the character counter 3 becomes "26" and the character display area designating circuit 4
When the signal Hc is output again, the display data register 17 again starts the shift operation in synchronization with the clock pulse CP, and as a result, the character data for one line stored in the display data register 17 ( A second line dot signal for (80 characters) is sequentially generated by the character generator 18 for each character data. Furthermore, the dot signal in units of 8 dots output from the character generator 18 is serially converted by the P-S conversion register 20 and sent to the CRT display section, so that each character in the first line is displayed on the CRT. A dot for the R1 line is displayed. In this way, dot display control is performed sequentially for the display lines (LO to L8). Then, the dot display of the display line (LO-L8) is completed, the count content of the line counter 7 becomes "10", and the content of the character counter 3 becomes "106" (displaying the last character in one line). position), the decoder 11 outputs a fault signal (HALT), which causes the CPU to input the next start address (ST-A) to the address counter 15.
Send to.

Furthermore, when the count content of the line counter 7 reaches the final count value, that is, "11", the output of the decoder 12 becomes 61'', character data for one line is read out from the data memory 16 again, and this character data is displayed sequentially. The data is updated and stored in the data register 17. By repeating this operation, the character display area DI of the CRT is
-C contains one page (8 pages) stored in the data memory 16.
Character information (0 characters x 24 lines) is displayed, and a one-dot mark for page recognition is always displayed in the page recognition display area PA-C on the first page and first line. Next, we will explain the page recognition information display operation when the character data on the first line of the second page of the data memory 16 is displayed at a certain display line position on the CRT. data transfer period), the address counter 15 is 192.
Control is performed in increments starting from address 0, and data in the first row of the second page of the data memory 16 is sequentially read character by character by the address designation of the address counter 15 and stored in the display data register 17 in sequence.

When the count value of the address counter 15 becomes "1984" during this data transfer, that is, when the 64th character of the first line of the second page of the data memory 16 is specified, this address data A page recognition signal P2 is output from the decoder 101 of the page recognition display circuit 100, and this signal P2 is supplied to the set input terminal (S) of the flip-flop 1031 via the OR circuit 102, and also to the set input terminal -f of the flip-flop 1032. -<S), each flip-flop 10
3, 1032 are set together. Thereafter, one line of character data (80 characters) is stored in the display data register 17 in the same manner as described above, the signal Hc of the character display area designation circuit 4 is cut off, and the character counter 3 further starts counting operation. The line counter 7 is incremented by the carry signal (L, l →
LO), and the line counter 9 is also incremented by the carry signal of the line counter 7. This causes the display period to enter the next line, that is, the first line of the second page.
After that, the count content of character counter 3 becomes “
26'' and the signal Hc is output from the character display area specifying circuit 4, the L level at that time. - When the content of the dot counter 2 becomes "2" (D2) within the period H26, the first page recognition dot display information is output from the AND circuit 1041, and this is output from the OR circuits 105 and 2.
The first line (LO) of the page recognition display area PA-C corresponding to the line position where the character information of the first line of the second page of the display screen is displayed,
It is displayed at the third dot (D2) position. Furthermore, when the content of dot counter 2 becomes "5" (D5), AND circuit 1
04 outputs second page recognition dot display information, which is sent to the CRT display section via OR circuits 105 and 21 and displayed at the sixth dot (D5) position on the same line (LO). In this way, the page recognition display of the second page is performed by the two dot marks. Thereafter, characters are displayed for one line of data stored in the display data register 17 in the same manner as the character display operation described above. In the above-described embodiment, the page recognition display area PA-C is provided on the left side of the screen, but the page recognition display area PA-C is not limited to this, and may easily be provided on the right side.

Further, the display form for page recognition is not limited to displaying the number of dots, but may also be recognized and displayed using, for example, numbers or symbols. Further, in the above embodiment, a dot mark is attached on the same line to display page recognition, but the present invention is not limited to this. For example, a dot mark is attached on the same dot line (Di) to display the page number. You may. Further, in the above embodiment, the storage capacity of the data memory is set to two pages for convenience of explanation, but the present invention is not limited to this, and the present invention can be easily adopted as an arbitrary multi-page configuration. , the detection means for the page recognition signal (P1...) is not limited to the above configuration, and can be modified in various ways without departing from the gist of the present invention. As detailed above, according to the present invention, a character display device is equipped with a memory capable of storing display information for multiple screens divided into pages, and has a functional configuration capable of recognizing and displaying information spanning pages. By simply adding a simple configuration without storing page number information in memory, it is possible to reliably and easily recognize and display the page number corresponding to the displayed information, thereby preventing damage to the display function. Therefore, it is possible to provide a highly practical page information display method in a character display device that allows the page for display information to be clearly recognized without any confusion.

[Brief explanation of the drawing]

The figure is for explaining one embodiment of this invention.
The figure is a circuit configuration diagram, and Figure 2 is a diagram showing an example of page recognition information.
Figure 3 is a diagram for explaining the display position on the display screen, Figure 4 is a diagram for explaining the dot display position on the first page, and Figure 5 is a diagram for explaining the character information display period in the one-line display period. In addition, FIG. 6 is a signal timing diagram showing a data transfer period. 1... Clock generator, 2...
Dot counter, 3...Character counter,
4...Character display area designation circuit, 5...
...Delay circuit, 6, 13, 14, 19, 102, 10
41,1042...AND circuit, 7...
・Line counter, 8...Line display area designation circuit, 9...Line counter, 10...Line display area designation circuit, 11, 12, 101...・Decoder, 15...Address counter, 16...
...Data memory, 17...Display data register, 18...Character generator, 2
0...P-S...Conversion register, 21
, 105...OR circuit, 100...page recognition display circuit, 1031, 1032...flip-flop.

Claims (1)

[Claims] 1. A function that has a memory that can store display information spanning multiple pages and can recognize and display information read from the memory across multiple pages within a predetermined information display area excluding a part of the display screen. means for generating page recognition information specific to a page area of information to be displayed when recognizing and displaying the contents of the memory in the character display device of the present invention; and page recognition information generated by the means. A method for displaying page information in a character display device, comprising means for recognizing and displaying the information in a specific area outside the information display area corresponding to the information display position of the corresponding page area read from the memory.