JPS5938608B2 - Data transfer control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a stop control method, and in particular, in an input/output control device controlled by a microprogram, when data is being transferred between the input/output control device and another,
The present invention relates to a data transfer control method that allows data transfer to continue without stopping even if a stop signal is received from another source.

Recent data processing systems are configured to include a processor in an input/output control device and to control a plurality of input/output devices connected to the input/output control device.

For example, as shown in FIG.
Input/output devices 2-1, 2-
2 are connected to each other, and these input/output devices 2-1 and 2-2 are configured to be controlled by the processor 3.

Now, data transfer is being performed between the input/output device 2-1 and the input/output control device 1, and in this case, this data transfer is controlled by the processor 3 controlled by a microprogram, and the input/output device 2-1 It is assumed that the data transferred from -1 is temporarily held in buffer 4.

In this way, when data is being transferred between the input/output device 2-1 and the input/output control device by the processor provided in the input/output control device and controlled by the microprogram, troubleshooting, etc. For some reason, the processor 3 may be unconditionally stopped by a stop signal from the maintenance panel.

Therefore, if the program is unconditionally stopped by the stop signal as described above during data transfer, the processor will no longer operate, and the input/output control device 1 and input/output device 2-1 will no longer operate. data transfer will no longer occur. This causes over-runs and under-runs, and in some cases, errors. Therefore, when the processor 3 is stopped for debugging or troubleshooting, a secondary error may occur. Therefore, in the present invention, in order to improve such drawbacks, when data transfer is performed where it would be a problem if the processing stops midway, stop inhibit control is performed in advance as shown in FIG. It is an object of the present invention to provide a stop control method that performs stop enable control to then perform data transfer step A and release the stop inhibit control after the data transfer step A is completed.

And for this purpose, the stop control method of the present invention. In the stop control method of microprogram-controlled input/output control equipment. Status display means 6 for indicating whether the status display means is in a data transfer state or a stoppable state 6 Processing stop prohibition signal generation means for instructing the state display means to display the data transfer state 6 Commanding the state display means to be in a stoppable state Only when the processing stop signal generating means 6 which instructs the processor to stop, the processing stop signal generating means 6, and the processing stop signal generating means generate a processing stop signal, and the status display means is displaying a stoppable state. The present invention is characterized in that it includes gate means for generating a signal for stopping the processor.

An embodiment of the present invention will be described below based on FIG.

In the figure, 5 is a first flip-flop which operates as a status display means. 6 is a second flip-flop which operates as a processing stop signal generating means; 67 is a NAND circuit; and 8 is a stop key.

A processing stop inhibit signal ON STOPINH is applied to the first flip-flop 5 prior to data transfer in which the processing cannot be interrupted midway.

When this processing stop prohibition signal is applied to the set terminal, the Q output of the first flip-flop 5 becomes [0]. This [0] is transmitted to one output terminal of the NAND circuit 7. The above process is then completed. When it is no longer necessary to prohibit processing interruption. Processing stop prohibition release signal OFFSTOPI to cancel the above processing stop prohibited state
NH is applied to the reset terminal of the first flip-flop 5. As a result, the Q output of the first flip-flop 5 is inverted from "O" to "1". A stop key 8 is connected to the second flip-flop 6.

When the fixed contact 8-1 of the stop key 8 is grounded. Output terminal Q of second flip-flop 6
``0'' is generated. This is transmitted to the other input terminal of the NAND circuit 7. and. When the fixed contact 8-2 of the stop key 8 is grounded. The output terminal Q of the second flip-flop 6 outputs "1". The stop key 8 is provided, for example, on a maintenance panel.

When maintenance personnel wish to stop the processor for reasons such as troubleshooting, they operate the stop key 8. Now, as shown in FIG. 1, when executing data processing A shown in FIG. When the data processing A executes a data transfer that would be inconvenient if the data processing A stops in the middle of the execution process, the data processing A must be performed before the data processing A is executed. As shown in A-1 of Figure 2. The program generates a processing stop inhibit signal 6, and the process stop inhibit signal ON STOPINH is printed on the set terminal of the first flip-flop 5 shown in FIG.

As a result, "o" is output from the output terminal 0 of the first flip-flop 5, and this "o" is transmitted to the NAND circuit 7. Therefore, while the above-mentioned "0" is being transmitted, the NAND circuit 7 outputs "1" regardless of the output from the second flip-flop 6. 1 of this NAND circuit 7 is the run (RU) of the processor 3 shown in FIG.
N) It is used as a signal to set the signal.
In other words, while the NAND circuit 7 is outputting "1", the processor 3 continues the data transfer operation and never stops.Therefore, during the execution of data transfer A in FIG. Operate the key 8 to connect the fixed contact 8-
2 is grounded. Even if an attempt is made to stop the operation of the processor 3, the processor 3 does not stop as described below.

That is, based on the grounding of the fixed contact 8-2, "1" is generated from the output terminal Q of the second flip-flop 6.
As above. Since "0" is continuously output from the output terminal Q of the first flip-flop 5, the NAND circuit 7
outputs "1" as before, and processor 3 executes data processing A. And when data transfer A is finished,
As shown in Figure 2 A-2. A processing stop prohibition release signal is generated by the program, and is the processing stop prohibition release signal? ΩFS
TOPlNH. It is applied to the reset terminal of the first flip-flop 5 shown in FIG.

As a result, [1] is output from the output terminal of the first flip-flop 5. When the processor is performing data transfer in this state, in order to stop the operation of the processor 3 at the maintenance panel, the fixed contact 8-2 is grounded in FIG. "1" is output from.

Therefore, the NAND circuit 7 has two input terminals each with “1”.
” is applied. This time, it outputs "o" 6, which causes the processor 3 to temporarily stop its operating state.
Thus, for example, inspections such as troubleshooting can be carried out by maintenance personnel. And this inspection is completed. Switch the stop key 8 so that the fixed contact 8-1 is grounded again. When "0" is outputted from the output terminal Q of the second flip-flop 6, "1" is outputted again from the NAND circuit 7, and the processor 3 executes data processing.

Generally, a processor in an input/output control device is configured as shown in FIG. 4, for example.

In FIG. 4, the arrow side of the line X--X is the processor side. Now, due to a command from the control circuit 10. The instruction at the address written in the instruction address register 15 is read from the control storage 11,
This is output to the Bj operation register 12.
6 of the output to this operation register 12
The instruction code is normally transmitted to the control circuit 10, and based on this, the control circuit 10 performs necessary control operations. Also, among the outputs written in the operation register 12. The normal data portion is processed by the arithmetic circuit 13, and the results are stored in the memory 14 and . It is written in external registers 18, 19, 20, etc. Also 6 control storage 11
If the instruction read from the memory is a branch instruction, it is written into the instruction address register 15, and the control storage 11 is thereby read. Normally, the address written in the instruction address register 15 is . It is incremented by +1 by the +1 counter 16, and the contents of the control storage 11 are continuously read out. The control circuit 10 not only controls the arithmetic circuit 13 but also controls the gate 17 and performs various other control operations.The control circuit 10 receives a control signal from an external gate circuit 21. For example, the processor is configured to run when a run signal is applied and to stop when a stop signal is applied.

How to configure a processor configured in this way to execute the run/stop control shown in the present invention. Section 18-1 of external register 18 outside the processor is placed in first flip-flop 5 shown in FIG. Gate circuit 2
1 corresponds to the NAND circuit 7 as well. That is, from the control storage 11 to step A- as shown in FIG.
1. A microinstruction such as A-2 is read. When executed, the stop prohibition signal and the 6-process stop prohibition release signal b{ are written in the section 18-1. By transmitting the corresponding signal to the gate circuit 21, the above control can be executed. Therefore, as explained above, the present invention is very effective when executing data transfers where it would be a problem if the processing stops midway through, and prevents the occurrence of overruns or underruns. It can be prevented.

Thus performing the data transfer very efficiently/)
As a result, data processing efficiency can be improved.

[Brief explanation of drawings]

Figure 1 is an explanatory diagram of the input/output pedestal device and the input/output device;
The diagram is. Example 6 of the program used in the present invention, Part 3
FIG. 6 shows the configuration of an embodiment of the present invention. FIG. 4 shows a configuration diagram of a processor.

Claims (1)

[Claims] 1. In a stop control method for an input/output control device controlled by a microprogram, a status display means indicating whether the data transfer state or a stop possible state is present, and a processing stop prohibition signal that instructs the state display means to display the data transfer state. generation means, release signal generation means for instructing the status display means to be in a stoppable state, processing stop signal generation means for instructing the processor to stop, and the processing stop signal generation means generating a processing stop signal. A stop control system further comprising gate means for generating a signal for stopping the processor only when the state display means indicates a stoppable state.