JPS5938646B2 - signal detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal detection circuit for distinguishing signal blocks from noise blocks.

Conventionally, as a data format in a magnetic tape device, a signal sequence that continues for a certain period of time, that is, a signal block consisting of a preamble, data, and postamble, as shown in FIG. 1, is often used. When reading the input signals forming these signal blocks, the interblock gap (IBG)
) may be mixed in with a noise block, it is desirable to identify the signal block as a noise block at least at the preamble stage, check the signal state, and then start data demodulation. For this reason, a signal block detection circuit for distinguishing signal blocks from noise blocks is required, but no circuit of this type that can handle digital input signals has conventionally been found.
SUMMARY OF THE INVENTION An object of the present invention is to provide a signal detection method that can distinguish digital signal blocks from noise blocks with high precision and detect correct signal blocks.

In order to achieve the above object, the signal detection circuit of the present invention includes a first counter that detects whether a period of a read signal of a signal block recorded on a magnetic tape is within a first specified time; a second counter that detects that the input of the read signal continues for a second specified time longer than the first specified time; and a second counter that is reset by the detection output of the second counter, and The counter is reset when the first counter detects that the period of the signal is longer than the first specified time.

The present invention will be described in detail below with reference to examples.

FIG. 2 is an explanatory diagram showing the configuration of an embodiment of the present invention.

In the figure, numerals 11 and 14 are counters, and the counter 11 directly inputs an input counting pulse 1 consisting of a clock pulse, and the counter 14 inputs an output 4 via an AND circuit 13 for counting. 12 and 15 are asynchronous flip-flops.

Next, the input signal 2 forming the digital signal block is branched and applied to the reset terminal of the counter 11 and the set terminal of the flip-flop 12, and its output is input to the AN
Input to D circuit 13. The counter 11 is reset every time the input signal 2 is generated and starts counting, and when the count value corresponding to the specified time (T1) is reached, an output 3 is generated and a flip signal is generated.
It is connected to the set terminal of flip-flop 12 and branched to the set terminal of flip-flop 15. The counter 14 starts counting by resetting the output 3, and when the count value corresponding to the specified time (T2) is reached, output 5 is generated, and the output is set by inputting it into the set terminal of the flip-flop 15. By resetting with the aforementioned output 3, a signal block detection output 6 is obtained. FIG. 3 is a time chart showing operating waveforms of various parts for an example of an input signal in the configuration of FIG. 2.

It is assumed that the input counting pulse 1 is the clock pulse shown in the figure, and the input signal 2 is a digital signal pulse consisting of five pulses arranged at the shortest interval.

That is, the counter 11 is reset by the first pulse of the input signal 2 and starts counting, but after a specified time (T1
) is selected to be larger than the shortest interval, so the count value is (
Before reaching T1), it is reset by the next pulse and does not generate output 3, and in the same way, it is set by a pulse and the counting is repeated, but no output 3 is generated, and when it starts to reach the last pulse, the count value is (T1) and generates output 3. On the other hand, the first pulse of the input signal 2 sets the flip-flop 12, so that the output 4 of the AND circuit 13 is input to the counter 14 as a counting pulse 4 as shown. Since the counter 14 is preset by the output 3 reset signal of the previous stage, it immediately starts counting and repeats the input signal for a specified period of time (for example, indicating that the input signal has been repeated about three times).
When T2) is reached, the output 5 as shown is generated, the flip-flop 15 that was previously set by the output 4 of the previous stage is set, and the detection output 6 as shown is taken out from the rising output terminal. . This output is reset by the output 3 generated by the counter 11 when the count value reaches (T1) by the last pulse, and the waveform of the detection output 6 shown in the figure is obtained. In this case, if the length of the signal block is a, the detection output length b is expressed as b-a+(T2-T1), and the specified time (T
By making 2) slightly larger than (T1), the detection output length b becomes equal to the signal block length a for a certain period of time (T1) and (T2).
) is added as a margin. Here, if a noise pulse N is input before the five data pulses, the data pulse and the noise pulse are distinguished as follows. That is, if this noise pulse N is separated from the first pulse of the data pulse by more than a specified time (T1), the counter 11 is reset by the noise pulse N, and the counter 11 is counted and reset as soon as the specified time (T1) is reached. Outputs signal 3. However, the counter 14 counts when the noise pulse N is input, but since (T2) is selected longer than the specified time (T1), the counter 14 starts counting by the reset signal 3 before reaching the selected time (T2). 14 is set, so there is no output 5. Therefore, noise pulses can be distinguished from data pulses. If the signal block includes not only pulses with the shortest interval but also parts with wide pulse intervals as in the embodiment shown in FIG. 3, the specified time (T,) must be selected accordingly. As explained above, according to the present invention, in order to distinguish the digital input signal forming the signal block from the noise block, two counters are used to count the specified times (T1) and (T2). Since the detection output of the signal block can be obtained with high discrimination accuracy and the circuit is relatively simple, it can be effectively used for the above-mentioned purpose.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of the data format of a magnetic tape, FIG. 2 is an explanatory diagram showing the configuration of an embodiment of the present invention, and FIG. 3 is a time chart explaining the operation of the embodiment of FIG. Medium, 1
1 and 14 are counters, 12 and 15 are flip-flops,
13 indicates an AND circuit.

Claims (1)

[Claims] 1. A first counter that detects whether the cycle of a read signal of a signal block recorded on a magnetic tape is within a first specified time; a second counter that detects that the period of the read signal continues longer than the first specified time; and a second counter that detects that the period of the read signal is longer than the first specified time; A signal detection circuit comprising means for being reset in response to detection by the first counter.