JPS5939057B2 - Register control method of calculator with Katsuko calculation function - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control method for a computer with a cut-off calculation function, in which a cut-off register necessary for performing cut-off calculations can also be used as an independent memory.

Conventionally, calculators with a Katsuko function that can perform Katsuko calculations have prepared a large number of registers dedicated to Katsuko to execute Katsuko calculations, and there are registers for calculations and memory registers for independent memory. In addition to the above, a large number of registers were required.

Therefore, in the past, when attempting to perform a cut-off calculation using a large number of cut-off registers, if the above-mentioned cut-off registers were used for memory, if the parenthesis calculation was performed with information first entered in the register, miscalculations could occur. There was a problem that the information in the above register would be erased. Therefore, the present invention makes full use of the available registers, provides efficient usage, and makes it possible to carefully protect the information already stored. Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram of the present invention. In the figure, N is the mansion key, and the signal from the mansion key is sent to the encoder EC.
The signal is input into the register X, is converted into a binary code, and is stored in the register X via the OR gate Glo. The data of this register X is displayed on a display section (not shown). In addition, there is also a register Y for executing operations including this register X.
, Z, but they are not shown for convenience of explanation, and the calculation execution is the same as that of a general computer, so the explanation thereof will be omitted. Further, M1 to M3 share the register for the cutter or the register for the independent memory, and the data of the register X is inputted through the gates G12, G14, and G16.

One input terminal of these gates G72, G74, and G16 receives input from input keys X→M1, X−■M2, X−)M3 or gates G, , G, 8, ,. Signals 04, 05, 0 from
6 is input. In other words, input key x → M1...
... are data input gates G42 and G1 when registers M1, M2, and M3 are used as independent memories.
4. It opens G16, and gates G17, G18, and G
19 inputs a signal that detects the presence or absence of data stored in registers M1, M2, and M3. For example, register M
If no data is stored in register 1, gate Gl2 is opened and signal 04 is output to transfer the data in register X to register M1. Detection circuits Ll, L2, L3 detect the presence or absence of data in registers Ml, M2, M3, and the detection signals are sent via inverters to gates Gl7,
It is input to Gl8 and Gl9. On the other hand, (K is an open cutter, which is used when performing calculations with a cutter, and the input signal from this cutter (K) is to sequentially transfer the data of register Forward.

In other words, (the signal from K is 1 through OR gate G3O)
The word pulse counter TC is applied as a start signal, and the pulse counter TC output terminals W1 to W3 output the signals in the order of Wl, W2, W3, and the gates Gl2, Gl in sequence.
4. Signals 01 to 03 to open Gl6 to gate G
Used from 1 to G9. Therefore, when the key (K) is pressed, the signals 01, 02, and 03 are output in sequence as shown in Figure 2.When the key (the first close key) is pressed, the signal 0 is output in the reverse order.
3, 02, 01 are output sequentially. Above signals 01, 02
, 03 are added to the gates Gl7, Gl8, and Gl9 described above, and therefore, the gates Gl2, Gl4, and Gl6 are sequentially opened in the relationship shown in FIG. However, register M
For example, if data is stored in registers Ml and M2, gates Gl7 and Gl8 will not open, that is, signal 06 will be output and only Gl6 will open and register data will be transferred. From the above explanation, if data is stored in registers M1 and M2 first, the data in register will be carried out. or,
Signals 04, 05, and 06 are also signals for setting flip-flops F1 to F3.

In other words, flip-flops Fl, F2, and F3 use register M as a cutter register, and
It is set when data is transferred to register M, and stores that data related to the cutoff calculation is stored in register M. However, when register M is used as an independent memory, flip-flops F1-F3 are not set even if data is stored in this register. Further, the storage signals of the flip-flops F1 to F3 are used as signals for reading data from the registers M1 to M3, and are applied to gates G2O, G2l, and G22. Signals 01, 02, and 03 are input to one of the gates G2O, G2l, and G22, respectively, and signals 07 to 09 are outputted and applied to gates G26, G27, and G28 via OR gates G23, G24, and G2. Therefore, if the flip-flop is set, the switch will close.
By pressing , the signal changes to 03,02 as explained earlier.
, 01, the gates G28, G2
7 and G26 are opened in this order, and the data in register M is transferred to register X via OR gate G2, and arithmetic operations are performed with other arithmetic registers. Here, signals 04-09
Since the signal is input to the reset terminal of the pulse counter TC via the gate G3l, the pulse counter TC stops counting and stops outputting the signal. Therefore,
When signal 09 is output, at that point, pulse counter TC stops operating, signals 01, 02, and 03 are not output, and flip-flop F3 is reset. Then, by pressing K, the gate G27 is opened, and the data in the register M2 is transferred to the register X.
At the same time as the calculation is executed, flip-flop F2 is reset. Furthermore, MRl, MR2, and MR3 in the figure are keys for reading data in register M when registers Ml, M2, and M3 are used as independent memories, and their input signals are OR gates G23, G24, G2, have been added to each.

Further, in the figure, FM is a computation end signal, and when this signal FM is output, the gate G32 is opened and the start signal from K is applied to the one word pulse counter TC. In the above configuration, now the register Ml
, M2 as independent memories, keys X-+M1, X-+M
It is assumed that data is stored by pressing 2.

Therefore, the operation will be described below by taking as an example the case where A×(B+C) is calculated. First, press the number key N to enter the value “A”.
Enter.

This value ``A'' is stored in register A start signal is applied to the pulse counter TC, and the gates Gl2, G are sequentially applied from the output terminals Wl, W2, W3.
A signal for opening l4 and Gl4 is output. here,
Since the registers Ml and M2 already contain data, Ll and L2 of the register data presence/absence detection circuits L1 to L3
The output of is 2, and gates Gl7 and Gl8 are closed.

Since the output signal of the detection circuit L3 is only O'', the signal 06 is derived from the gate Gl, the gate Gl6 is opened, and the contents A7 of the register X are transferred to the register M3.At this time, the register M3 is opened. Flip-flop F3 is set to store the fact that it is used as a function register.Also, by outputting signal 06, a count stop input is applied to the 1-word pulse counter TC, and the count pulse is stopped. To explain using the time chart shown in FIG.
1,02,03 but at time T. - during t1, from t1
During T2, signals 01 and 02 are sequentially output, but gates Gl7 and Gl8 are not opened and signals 04 and 05 are not output. Therefore, since the signal 03 is output between time T2 and T3, the gate Gl is opened and only the signal 06 is output. Therefore, gate Gl6 opens and data A'' of register X is transferred to register M3, and flip-flop F
3 is set. Subsequently, when the numerical value "B" is input, the data "B" is stored in the register X and displayed at the same time.

Then, by inputting the value ``C'', the value ``C'' is stored in register X and displayed, and the previous value ``B'' is
2 is transferred to and stored in another calculation register (not shown). After the above-mentioned operations, when the close button 1) K is pressed, B+C is executed in each calculation register, and the calculation result is stored in the calculation register.

Then, by deriving the computation end signal FM, the 1-word pulse counter TC operates via the gate G32,
The signals are output in the order of 03, 02, 01. As a result, as shown in FIG. 2, since the signal 03 is output during the time period T4 to T, the gate G22 is opened and the signal 09 is derived. Therefore, data A'' of register M3 is read out and transferred to register As mentioned above, if data A'' in register M3 is transferred to register
C) is executed, and the calculation result AX(B+C)'' is stored in register X and displayed.

Although this embodiment shows a case where there are three registers M, the present invention is not limited to this. Also, when all registers M are used for cutters, the data input to register Transferred to X.

Furthermore, CAU in the figure is a warning device, and when K is pressed and data is stored in all registers M1, M2, and M3, gate G33 is opened, and a signal is applied from this gate G33 to the warning device CAU. , the operator is informed that further cutlet calculations are not possible.This warning device CAU is designed to notify by display, blinking, or sound.As explained above, the register control method of the present invention For example, you can make effective use of the registers you have, for example, if you use some of them as registers for independent memory, when performing a calculation with a cut-off, you can do it without inputting data to the registers for independent memory. Data can be input into an empty register, ensuring data protection and eliminating miscalculations.

Therefore, it is possible to provide an easy-to-use calculator that values data.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining the register control system of the present invention, and FIG. 2 is a timing chart related to FIG. 1. Gl2, Gl4, Gl6: Register data input gate, Ml, M2, M3: Register for cutter or independent memory, Ll, L2, L3: Data presence/absence detection circuit, F
l, F2, F3: Flip-flop for memory in the cutlet function (K: open cutter) K: closed cutlet.

Claims (1)

[Claims] 1. In a computer that has a Katsuko key, is provided with a large number of registers for Katsuko calculations other than registers for arithmetic operations, and is equipped with a Katsuko calculation function, for inputting data into the registers in order to use the above-mentioned large number of registers as independent memory. is provided with an input section that opens the input gate section of the register, detects the presence or absence of data in the large number of registers, and uses this detection signal to open the input gate section of only the register that does not store data among the large number of registers; By pressing the Open Katsuko key to perform Katsuko calculation, the necessary input data etc. are stored in the empty registers in order according to the press of the above Open Katsuko key, and by pressing the Close Katsuko key, the data is transferred from the register that stored the data related to the above Katsuko calculation. A register control method for a computer with a katsuko calculation function that reads out the data, transfers it to the arithmetic register, and executes the arithmetic operation.