JPS5953580B2 - Random number generation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a random number generation method in, for example, a small electronic calculator.

Generally, a sequence of numbers having equal probability and irregularity is called a random number, and methods for generating such random numbers include those using calculations and those using counters.

In the former, random numbers are obtained by sequentially calculating predetermined initial values using methods such as the square counting method, aggregation congruence method, and mixed congruence method, and in the latter method, for example, the counter is set to a relatively fast clock. The counter is constantly driven by a constant count, and the contents of the counter are taken out as necessary and used as random numbers. However, in the former method, it is difficult to set the initial value because the same random number will be generated if the initial value is the same.
Another disadvantage is that the control commands and the like are complicated due to the complicated calculations. Furthermore, in the latter method, highly accurate random numbers can be easily obtained by making the clock for driving the counter relatively fast, but on the other hand, a dedicated counter for random number generation is required, and the circuit configuration becomes complicated. I had a lot of flaws.
On the other hand, in small electronic calculators, various arithmetic processes are performed through arithmetic circuits, but the arithmetic circuits are not used particularly during non-arithmetic processing, which is inefficient.

The present invention has been made in view of the above-mentioned circumstances, and is a random number generator that generates random numbers by effectively utilizing arithmetic circuits that are not used during at least non-arithmetic operations, and that makes it possible to retrieve the random numbers as needed. It provides a method.

An embodiment of the present invention will be described below with reference to the drawings.

Figure 1 shows its configuration. In the figure, 1 is the random number key "
It is truly a key input unit equipped with numeric keys, numeric keys, various function keys, etc., and sends key input signals corresponding to each of the keys to the encoder unit 2. This encoder section 2
is to encode the key input signal from the key input section 1, and for the numeric key, the key presence signal is encoded by the control section 3.
Then, the set number data is sent to one end of the AND circuit 41 of the gate circuit group 4, and a key presence signal is supplied to the control section 3 for the random number key digit rl, and the flip-flop circuit 5 is set. It is supplied to the input terminal S and the OR circuit 6, and further, the function data for each function key is supplied to the control section 3. The control section 3 outputs a numeric instruction, an arithmetic instruction, or a control signal to gate circuit groups 7, 8, and 9, which will be described later, according to the output signal of the encoder section 2, and transfers the numeric value, arithmetic instruction, and random number. When the operation of
It also controls the code generator 1 which outputs code signals such as . The above-mentioned numeric instruction and arithmetic instruction are applied to the set input terminal R of the flip-flop circuit 12 via the OR circuit 6, and the instruction end signal is applied to the set input terminal S. The set side output terminal Q of this flip-flop circuit 12
The output signal is supplied to one end of the OR circuit 71 of the gate circuit group 7 and one end of the OR circuit 81 of the gate circuit group 8, and is also supplied to the AND circuit 91 of the gate circuit group 9 and the inverter 9.
2 to one end of the AND circuit 93, and further supplied to the reset input terminal R of the flip-flop circuit 5. The output signal of the set side output terminal Q of the flip-flop circuit 5 is supplied to the one-shot circuit 13. This one-shot circuit] 3 outputs an output for one word time when the flip-flop circuit 5 enters the set state in accordance with a clock signal φW outputted every one word time (eight digital times in the present application) from a timing signal generator (not shown). The output signal is supplied to one end of the AND circuit 42 and the Soar circuit 43 of the gate circuit group 4, and is also supplied to the AND circuit 72 of the gate circuit group 7 and the AND circuit 82 of the gate circuit 8. Incidentally, the digital signals D1 to D8 are sequentially output from a timing signal generating section (not shown) every word time, and the AND circuit 72 is closed at the timing of D1+D2, and the AND circuit 82 is closed at the timing of D1+D2. will be done. The output signal of the AND circuit 72 is output from the OR circuit 71.
The code signal is applied to the AND circuit 73 to which the code signal is supplied from the code generating section 11 via the code generating section 11, and controls the opening and closing of the AND circuit 73. This AND circuit 73 output signal is supplied to the input terminal a of the arithmetic circuit 10. On the other hand, 4 is an 8-digit (8-digit) shift register for counting random numbers and storing calculation data, and 7-digit (7-digit) registers 14a and 1
The output of the register 14a is supplied to the AND circuit 83 of the gate circuit group 8, and its output signal is supplied to the input terminal b of the arithmetic circuit 10 and then to the 4-input terminal a. An operation is performed on the supplied data. The calculation result is then output to the AND circuit 91 of the gate circuit group 9. It is written into the shift register 14 via the OR circuit 94. Furthermore, when no calculation is performed, the contents of this shift register 14 are the AND circuit 93 and the OR circuit 9.
The memory is retained while being recirculated via 4. On the other hand, the operation result of the arithmetic circuit 10 is written into the shift register 15 via the AND circuit 42 and the OR circuit 44 of the gate circuit group 4, and the numeric data output from the encoder section 2 is written to the control section 3. AND circuit 4 of gate circuit group 4 whose opening/closing is controlled by a numeric command output from
1. This shift register 15 is composed of a 7-digit register 15a and a 1-digit register 15b, similar to the shift register 14 described above. The contents are recirculated via an AND circuit 45 and an OR circuit 44 whose opening and closing are controlled by the output signal of the NOR circuit 43 of the gate circuit group 4, and the output is sent via a display section (not shown) and the gate circuit group 8. The signal is sent to the arithmetic circuit 10.Next, the operation of the present invention configured as described above will be explained using the key operation ``METO T KAMURA KK KARU! Tsukasa'' as an example.

Figure 2 shows shift registers 14 and 15 that correspond to key operations.
This indicates the state of First, when no key of the key input section 1 is operated, that is, during non-operation, the flip-flop circuit 12 is activated as shown in the timing chart of FIG.
is in the set state, so the output signal "゜1" of the set side output terminal Q is sent to the AND circuit 73 via the OR circuit 71 of the gate circuit group 7, and to the AND circuit 83 via the OR circuit 81 of the gate circuit group 8. Since the voltage is applied to one end, the control unit 3
According to the command of the code generator] 1, the code signal “1” is generated.
(0001 in binary) is supplied to the input terminal a of the arithmetic circuit 10 via the AND circuit 73 at the timing D1, and the contents of the shift register 14 are supplied to the input terminal a of the arithmetic circuit 10 via the AND circuit 83. It is supplied to input terminal b, and addition of "+1" is performed in arithmetic circuit 10. On the other hand, the output signal "1" at the output terminal Q of the flip-flop circuit 12 in the set state is the AND circuit 91 of the gate circuit group 9.
The signal is applied to one end of the signal, and is inverted by the inverter 92 and applied to the AND circuit 93 as "0". will be written to.
Thereafter, in the same manner, the contents of the shift register 14 are sequentially incremented by "+1" every word time, and counted like a counter. Next, as shown in FIG. 2, when the numeric key 2 is operated, the encoder section 2 supplies a key presence signal in response to the numeric key operation to the control section 3, which outputs a numeric command. The numeric instruction sets the flip-flop circuit 12 through the OR circuit 6 as shown in FIG. The output signal of this flip-flop circuit 12 is “
0'', the AND circuits 73 and 83 are closed, and the contents of the shift register 14 and the code signal "l" from the code generator 1 are no longer supplied to the arithmetic circuit 10. Further, the output signal "O" of the flip-flop circuit 12 becomes "1" through the inverter 92 of the gate circuit group 9,
Since the voltage is applied to one end of the AND circuit 93, the contents of the shift register 17 are recirculated via the AND circuit 93 and the OR circuit 94 as shown in FIG. At the same time, the numeric command output from the control section 3 is supplied to the AND circuit 41 of the gate circuit group 4. The numerical data "2" is written to the shift register 15 via the AND circuit 4] and the OR circuit 44 as shown in FIG. When this numeric processing operation is completed, the numeric command is no longer output from the control section 3, and since the output signal of the one-shot circuit 13 is also "0", the output of the NOR circuit 43 of the gate circuit group 4 is "1". Then, the AND circuit 45 is opened, and the contents of the shift register 15 are held while being recirculated via the AND circuit 45 and the OR circuit 44, and an instruction is issued from the control unit 3 indicating that the arranging instruction has ended. The end signal is applied to the set input terminal S of the flip-flop circuit 12, and the flip-flop circuit 12 is put into the set state again.Therefore, the output signal at the output terminal Q of this flip-flop circuit 12 becomes "1", and as described above, the shift register The contents of 14 are sequentially added to the code "1" from the code generator 11 in the arithmetic circuit 10, and the count is increased as shown in FIG. Next, when the key is operated, the encoder section 2 supplies function data corresponding to the key to the control section 3. An arithmetic instruction is output from the control section 3, and the flip-flop circuit 12 is reset via the OR circuit 6 as shown in FIG. 2, and the content "2" of the shift register 15 is transferred to another shift register (not shown). (The contents are also held in the shift register 15). When the arithmetic instruction for the wrong key is completed, the control section 3 outputs an instruction end signal, and the flip-flop circuit 12 is set as shown in FIG. 3, and the flip-flop circuit 12 is set as shown in FIG. 2 until the next key operation. shift register 1 to
The contents of 4 are sequentially incremented by "+1". Then, when the 3 key is operated, a numeric command is output from the control unit 3 and "3" is written in the shift register 15 in the same way as when the 2 key was operated, and when the numeric processing operation is completed, the next The contents of the shift register 14 during non-operation until the key is operated are sequentially "+".
1” is done. Next, when a mouth key is operated, function data corresponding to the mouth key is sent from the encoder section 2 to the control section 3, and various control signals are outputted from the control section 3 and stored in the shift register (not shown). The arithmetic circuit 10 performs an arithmetic operation on the data "2" stored in the data "2" and the data "3" stored in the shift register 15, and the arithmetic result "6" is written into the shift register 15 as shown in FIG. It will be done. When the arithmetic processing operation is completed, the control section 3 outputs an instruction end signal as described above, and the addition of "+1" to the contents of the shift register 14 is performed sequentially. When the Kml key is operated, as shown in FIG. 3, a key presence signal for the random number key is supplied from the encoder section 2 to the control section 3 and the OR circuit 6, and the flip-flop circuit [2] is reset to the shift register]. The "+1" addition operation for the contents of 4 is stopped, and the keyed signal is supplied to the set input terminal S of the flip-flop circuit 5, so that the flip-flop circuit 5 is set as shown in FIG. As a result, a single pulse with a one-word time width is output from the one-shot circuit 13, and the AND circuit 42 of the gate circuit group 4 is opened.
The output signal of No. 3 is connected to one end of the gate circuit group 7 as a digital signal D.
1+D2 is supplied to one end of the AND circuit 72, and one end of the gate circuit group 8 is supplied to the other end of each of the AND circuit 82, which is supplied with the digital signal D1+D2. Therefore, the contents of the shift register 14 are ANDed at the timing of D1+D2. The block is written to the shift register] 5 via the circuit 83, the arithmetic circuit 10, the AND circuit 42 of the gate circuit group 4, and the OR circuit 44, and is output from the code generator 11 under the control of the control unit 3 at the timing of D1+D2. The ranking code is written into the shift register 15 via the AND circuit 73, the arithmetic circuit 42, and the OR circuit 44 of the gate circuit group 7. Therefore, a two-digit random number will be written into the shift register 15. Furthermore, as shown in FIG. 3, since the random number transfer operation from the shift register 14 to the shift register 15 is completed in one word time, an instruction end signal is output from the control section 3 and the flip-flop circuit 12
is set, and “+” is set for the contents of the shift register 14.
1'' addition is performed again. In the above embodiment, a case has been described in which the "+1" operation is always performed on the shift register 14 during non-operation, but this shift register 14 is also used to store operation data as described above. It is also possible to start adding "+1" from the stored data during non-operation after the calculation data is stored in this way.

Furthermore, the shift register 14 is not fixed for random number generation, and other unused registers can be used as appropriate random number generation registers.

Further, in the above embodiment, a case has been described in which a two-digit random number is extracted, but the present invention is not limited to a two-digit random number, and the number of digits can be set arbitrarily.

As explained in detail above, according to the present invention, there is no need for a dedicated counter or a fast counting clock for generating random numbers, and the random time during non-operation from the end of an operation to the start of the next operation is used. In addition, random numbers are generated by effectively utilizing registers and arithmetic circuits that are virtually inactive during non-operation periods, making it possible to obtain extremely high-precision random numbers and simplifying the circuit configuration. It has various advantages such as being able to be

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of an embodiment of the present invention, FIG. 2 is a state diagram of a shift register corresponding to the same key operation, and FIG. 3 is a timing chart corresponding to the same key operation. 1...Key input section, 2...Encoder section, 3...
Control unit, 10... Arithmetic circuit, 11... Code generation unit, 14, 15... Shift register.

Claims (1)

[Claims] 1. In an arithmetic device having a storage unit that stores at least a plurality of data and an arithmetic unit that performs operations such as four arithmetic operations based on the data stored in this storage unit, it is possible to determine whether or not the arithmetic unit is not in operation. A detection means for detecting the data and a code data generation means for generating code data based on the output of the detection means are provided, and when the detection means detects that the calculation is not in progress, the calculation section A random number generation method characterized in that code data generated by the code data generation means is sequentially added to data stored in a predetermined area within the storage section, and the addition result is output as a random number.