JPS5939068B2 - Signal enhancement circuit for pattern processing - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention obtains an image signal of a pattern to be inspected using a photoelectric conversion element or the like, divides this image signal into a mesh shape with an appropriate resolution, and further converts it into a digital signal. It is related to pattern processing equipment that performs recognition processing of patterns to be inspected using signals, and in particular, AD
The present invention relates to a signal enhancement circuit for pattern processing that enhances image signals of fine patterns during conversion.

Consider the case where two types of patterns as shown in FIGS. 1A and 1B are recognized using the above-mentioned type of pattern inspection apparatus.

FIG. 1A shows a normal black pattern on a white background, and FIG. 1B shows an abnormal pattern in which there are black printing scratches 1 and 2 in addition to the normal pattern. These two patterns must be identified as different, but print scratches 1 and 2
If the pattern is finer than the resolution, the presence of these printing flaws will be ignored and the patterns in FIGS. 1A and 1B will be considered to be the same. In order to make it clear that the two are different, it is necessary to divide the screen into meshes that have a resolution several times finer than those of these printing scratches 1 and 2. If the patterns that are locally different from the size of the pattern inspection area, that is, the printing scratches 1 and 2 in FIG. However, if the local pattern to be recognized is finer than the resolution, it is necessary to define the resolution extremely finely for the local pattern, which makes the configuration of the pattern inspection device extremely large and complicated, and In addition, there is a drawback that the processing time is significantly longer due to the increased amount of information to be handled. It is an object of the present invention to provide pattern processing that eliminates the above-mentioned drawbacks and emphasizes the signal of a local pattern so that it is possible to detect local patterns near the resolution or even finer without increasing the resolution as in the conventional method. An object of the present invention is to provide a signal enhancement circuit for use in the present invention. Still another object of the present invention is to provide a pattern in which, in multilevel AD conversion, a binary signal on the level side having more pattern features is emphasized preferentially. An object of the present invention is to provide a processing signal enhancement circuit.

The signal enhancement circuit of the present invention is used in a pattern processing device that obtains a digital image signal by dividing an image signal of a pattern to be inspected obtained from a successive scanning two-dimensional image sensor into a mesh shape at a predetermined image division frequency. a comparator that obtains a binarized signal by comparing it with a comparison level; a monostable multivibrator that generates a pattern stretching pulse having a longer pulse width; and a logic circuit that generates a signal-enhanced binary signal that is a combination of the pattern expansion pulse and the binary signal that is longer than the reference time, while leaving the binary signal that is longer than the reference time as it is. It is characterized by the fact that

Furthermore, for multi-level AD conversion, in the signal enhancement circuit of the present invention, the image signal is supplied to the plurality of comparators to extract the multi-level binary signal, and the multi-level 2 for a predetermined number of levels on the level side that has more pattern features among the binarized signals of
A digitized signal is supplied to a combination circuit of the monostable multivibrator and the logic circuit, and the signal-enhanced binary signal obtained from the logic circuit and a predetermined level side that includes more of the characteristic amount of the pattern are supplied. By adding the binary signal for the residual level other than the number level to the encoder and extracting the encoded binary signal, more features of the pattern can be extracted from the multi-level binary signal. The system is configured to preferentially emphasize the binarized signal on the level side.

The present invention will be explained below with reference to the drawings. First, the pattern inspection apparatus will be explained with reference to FIGS. 2 and 3.

In FIG. 2, when the object 3 to be inspected is fed on the conveyor table 4 in the direction of the arrow shown in the figure and reaches a suitable position within the field of view of the television camera 5, the position detector 6 detects this fact. The pattern inspection device 7 is notified. After detecting the position, the pattern inspection device images the pattern of the inspection object 3, converts the obtained one-screen image signal into a digital image signal using the AD conversion circuit 8 shown in FIG. Divide and sample. By simply digitizing and dividing the image, high frequency components higher than the image division frequency in the image signal are ignored. The image signal obtained by AD conversion is sent via the memory control circuit 9,
It is selectively stored in either the standard memory 10 which stores the pattern of non-defective products as a standard pattern or the sample memory 11 which stores the pattern of the object to be inspected. Reference numeral 12 in the figure indicates a camera control circuit, which supplies vertical and horizontal synchronizing signals to the television camera 5 to drive it, and also supplies these synchronizing signals to the determination control circuit 13.

The determination control circuit 13 also includes the output MSO of the mode switch on the operation panel 7a (FIG. 2) and the output of the position detector 6, and AD
It controls the operation sequence of the conversion circuit 8, memory Fblm circuit 9, arithmetic circuit 14 and determination circuit 15, which will be described later.
The memory control circuit 9 writes the AD conversion output to the standard memory 10 when the mode switch output MSO is in the standard pattern writing mode, and writes it to the sample memory 11 when the output MSO is in the judgment mode. When the pattern to be inspected is written into the sample memory 11 while the standard pattern is stored in the standard memory 10, the arithmetic circuit 14 compares and matches both patterns and calculates the degree of similarity between the two patterns. This similarity output is applied to the determination circuit 15 to determine whether the standard pattern of the pattern to be inspected is acceptable or not, and a determination output is obtained.
The present invention is configured to perform emphasis processing on the local pattern signal at the stage of the above-mentioned AD conversion so that local pattern signals having frequencies near or below the image division frequency can be detected.

Here, the abnormal pattern shown in FIG. 1B will be further considered. Figure 4A is the scanning line 1 of the abnormal pattern in Figure 1B.
The reference numeral 21 in the figure indicates a horizontal synchronization signal. Corresponding to the print flaw 1 in FIG. 1B, a print flaw signal 22 is generated in FIG. 4A. When this image signal is binarized using level d, a binarized image signal shown in FIG. 4B is obtained. As shown in FIG. 4B, the printing flaw signal 22 has a width τ
It is binarized as a pulse 23. Here, if the image division frequency Fs is 1>τ, the pulse 2 with a frequency 1/τ higher than the image division frequency Fs is applied to FS during image division.
3 does not appear, and a binarized image signal without printing scratches is obtained as shown in FIG. 4C.

In other words, the abnormal pattern shown in FIG. 1B is recognized in the same way as the normal pattern shown in FIG. 1A. the result,
It becomes impossible to detect printing flaws in subsequent processing. In the present invention, the minute pulses 23 caused by the above-mentioned printing scratches, etc. are emphasized by pulse width expansion to prevent their disappearance, as described below.

An example of such a signal enhancement circuit of the present invention is shown in FIG. Fifth
In the figure, an image signal 31 from a television camera 5
is supplied to the operational amplifier 32. External resistors R1 and R2 are connected to this amplifier 32, and the image signal 31 (R1
+R2) Take out the output amplified twice by 1R. This amplified output is applied to the 10 input terminal of the comparator 33, and compared with the comparison level E8 of the power supply 34 applied to the 1 input terminal to obtain a binary image signal A. This binary image signal A is sent to the delay element 3.
5 and the T input terminal of the retriker type monostable multivibrator 36. The delay element 35 has a delay time equal to the operation delay of the monostable multivibrator 36.
Note that when there is almost no delay in the operation of the monostable multivibrator 36, the delay element 35 may not be provided. Resistance R of the time constant circuit of monostable multivibrator 36
. and capacitor C. The value of is determined appropriately so that the pulse width t of the Q output pulse B of the monostable multipipulator 36 becomes several times the value 1/F8. The monostable multivibrator 36 operates at the falling edge of the comparator output A,
In other words, the output pulse B is obtained from the Q output terminal by operating at the falling edge of a negative direction pulse with a frequency several times the division frequency when the pattern changes from white to black. The output of the delay element 35, that is, the slightly delayed output of the comparison output A, and the monostable multivibrator output B are connected to the AND element 3.
7 and the obtained AND output C is supplied to the D terminal of a D-type flip-flop 38. A trigger input terminal T of this flip-flop 38 is supplied with an image dividing clock pulse D. Flip-flop 38 stores the value of the input at the D terminal on the rising edge of image division clock pulse D and holds the stored value until the next rising edge. The binarized image signal E obtained by dividing the image from the Q output terminal of the flip-flop 38
get. The operation of the signal enhancement circuit of the present invention will now be described in the case of the print flaw signal shown in FIG.

FIG. 6 is a signal waveform diagram showing the vicinity of the print flaw signal in FIG. 4, and FIG. 6A is the output A of the comparator 33,
The figure B shows the output B of the monostable multivibrator 36, the figure C shows the AND output C of the AND element 37, the figure D shows the image division clock pulse, and the figure E shows the output of the flip-flop 37, that is, the binary image signal. . A pulse portion 41 in FIG. 6A shows a printing flaw, and a wide pulse portion 42 shows a normal portion. Monostable multivibrator 36 responds to any falling edge in comparator output A, producing a pulse, each of pulse width t, as shown in FIG. 6B.
When these signals A and B are ANDed by an AND element 37, as shown in FIG. Output in width. This AND output c is taken out from the flip-flop 38 at the timing of the image division clock pulse D, and a binary image signal E in which the fine pattern portion has been enlarged is obtained. Next, Figure 1B
The operation of the signal enhancement circuit of the present invention in the case of the scanning line will be explained with reference to FIG.

7A, B, C, D and E are signals extracted from the same locations as A, B, C, D and E in FIG. 6, respectively.
Here, the printing scratch area consists of a large number of scratches, and the monostable multivibrator 36 is triggered every time a large number of printing scratch pulses occur, so that the monostable multivibrator 36 The Q output B lasts for as long as the printing scratch pulse portion, as shown in FIG. 7B. As described above, according to the signal enhancement circuit of the present invention,
Even if the pattern is minute, if it is binarized by the comparator 33, it will be expanded and emphasized into a signal with a pulse width t, and an abnormal pattern like the one shown in FIG. Detection can be performed.

It should be noted that fine parts of the normal pattern with a frequency of 1/t or more are also enlarged, but in that case, the standard pattern is also enlarged, so there is no problem in comparing both patterns. Note that the above is a case where there is a black scratch pattern on a white background, but if there is a white scratch pattern on a black background, the monostable multivibrator 36 in FIG. Similar signal enhancement can be achieved using an OR element and the Q output of flip-flop 38.

Next, an example in which the present invention is applied to 3-bit AD conversion is shown in the eighth section.
As shown in the figure.

In this example, the gradation between black and white is divided into eight levels corresponding to 3-bit AD conversion, and level 0 is assigned to white and level 7 is assigned to black. Among them, the pulse width is expanded for the four levels on the black side, and the pulse width is not expanded for the four levels on the white side. In FIG. 8, an image signal 51 is applied to a non-rotating amplifier 52, and its amplified output is supplied to each +input terminal of comparators 53-60. Voltage ECV] is applied to a voltage divider configured by series connection of resistors 61 to 68 having the same resistance value, and the voltage taken out from each of these resistors 61 to 68 is applied to one input terminal of each of comparators 53 to 60, respectively. supply The comparison outputs of the comparators 53 to 56 for the four white levels are sent to the encoder through delay elements 69 to 72, respectively. 7
3 to the lower 4 level input terminals. The comparison outputs of the comparators 57 to 60 for the four black levels are supplied to a combination similar to the above-described combination of the delay element 35, the retrigger type monostable multivibrator 36, and the AND element 37.
That is, the output of the comparator 57 is supplied to a combination of a delay element 74, a retricker type monostable multivibrator 75, and an AND element 76, and the output of the comparator 58 is supplied to a combination of a delay element 77, a retricker type monostable multivibrator 78, and an AND element 76. The output of the comparator 59 is supplied to the combination of the delay element 80, the retriker type monostable multivibrator 81, and the AND element 82, and the output of the comparator 60 is supplied to the combination of the delay element 83 and the AND element 82. It is supplied to a combination of a tricar type monostable multivibrator 84 and an AND element 85. The outputs of the AND elements 76, 79, 82 and 85 are sent to the encoder 73.
is supplied to the high-order 4-level input terminal. The encoder 73 generates a 3-bit encoded output based on the 8-level input binary signal from white to black. encoder 73
For example, 3
When level 1 and level 5 are input at the same time, the output is a coded signal of level 5. 2 forces of encoder 73, 2
1 and 22 outputs are connected to a D-type flip-flop 86, respectively.
It is supplied to the D input terminals of 87 and 88. An image dividing clock pulse 89 is supplied to each T input terminal of these flip-flops 86, 87 and 88. flip flop 8
6, 87 and 88, encoded image signals are extracted by dividing the image at the frequency of the image dividing clock pulse 89. That is, flip-flops 86, 87 and 88
From each Q output terminal, white is level O and black is level 7.
digital image signal outputs AO, Al and A2 are obtained,
From each Q output terminal, digital image signal outputs B2, Bl, and BO are obtained with level 7 for white and level O for black.
Generally, various print patterns are displayed using black information on a white mount, and when detecting differences in patterns or print stains, the black level side of the image is the characteristic.

Therefore, in the above example, the pulse widths of the four levels on the black level side are expanded, and the black level is emphasized and encoded. In addition, in the case of a printed pattern, the pulse width becomes narrower as the black level of the image signal increases due to the amplitude response of the television camera. For example, by scanning a black pattern 92 on a white background 91 shown in FIG.
For example, if an image signal as shown in Figure A is obtained and digitized at comparison levels from level O to level 7, a digital image signal as shown in Figure 10B is obtained. It can be seen that the pulse width becomes narrower. In other words, since the image signal on the black level side is a signal with a narrower pulse width than the original pulse width, by expanding the pulse width on the black level side as shown in FIG. 10C, the original pattern can be changed. can be approached. On the other hand, in the case of a white pattern on a black background, it is of course possible to configure the signal on the white level side to be emphasized as described above.

In this case, the polarity of each part in FIG.
It is sufficient to shift each comparison level of 0 in the negative direction. Furthermore, it is of course possible to perform pulse width modulation not only for a part of the multi-valued image signal, that is, for the level side information containing a large amount of features, but also for all levels. As is clear from the above, according to the present invention, when a pattern is finer around or finer than the resolution of pattern division, that is, when the spatial frequency is around or higher than the frequency of pattern division, fine patterning can be achieved without further increasing the resolution. Features of patterns can be extracted.

Furthermore, according to the present invention, fine patterns can be detected without particularly increasing the resolution, so unlike conventional methods, the configuration of the device becomes complicated to increase the resolution, and furthermore, the processing time increases due to the increase in the amount of information. It does not have the disadvantage of becoming long. That is, the configuration of the device is significantly simplified, a pattern inspection device can be realized at low cost, and processing time is also shortened. In addition, the present invention has the advantage that after signal enhancement, a simple method such as pattern matching can be used as an algorithm for a subsequent pattern matching test.

[Brief explanation of the drawing]

FIGS. 1A and 1B are pattern diagrams showing a comparison of normal patterns and abnormal patterns handled by the present invention, and FIGS.
The figure is an explanatory diagram of the outline of pattern inspection, FIG. 3 is a block diagram showing an example of the configuration of the pattern inspection device, and FIG. 4A
, B and C are signal waveform diagrams showing the image signal obtained by scanning the abnormal pattern in FIG. A circuit layout diagram showing an example of the signal enhancement circuit of the present invention, FIGS. 6A, B, C, D, and E show the operation of each part of the circuit layout shown in FIG. 5 in the case of the print flaw signal in FIG. 4. FIGS. 7A, B, C, D and E are signal waveform diagrams respectively showing the operation of each part of the circuit arrangement in FIG. 5 in the case of a large number of printing flaw signals. FIG. A circuit layout diagram showing another example of 3-bit AD conversion, FIG. 9 is a diagram showing an example of the pattern, and FIG. 10A
, B and C are signal waveform diagrams respectively showing a photoelectrically converted image signal by the scanning line 1 of the pattern shown in FIG. . 1, 2... Printing scratches, 3... Inspection object, 4... Transport platform, 5... Television camera, 6...・Position detector, 7...-Pattern inspection device, 7a... Operation panel, 8...
...AD conversion circuit, 9...Memory control circuit, 10...Standard memory, 11...
sample memory, 12...camera control circuit,
13... Judgment leg circuit, 14... Arithmetic circuit, 15... Judgment circuit, MSO...
Mode switch output, 21...Horizontal synchronization signal,
22...Printing flaw signal, 23...Printing flaw pulse, 31,51...Image signal, 32,52
...Normal rotation amplifier, 33, 53-60...
・Comparator, 34... Comparison level power supply, Rl, R
2.RO. ．． ．． ...Resistance, CO...Capacitor, 35,69-72,74,77,80,83...
...Delay element, 36, 75, 78, 81, 84...
...Retriker type monostable multivibrator, 37,
76, 79, 82, 85...AND element, 38
, 86, 87, 88... D-type flip-flop, 61-68... Voltage dividing resistor, 73...
... Encoder, 89 ... Image division clock pulse, 91 ... White background, 92 ... Black pattern.

Claims (1)

[Scope of Claims] 1. A pattern processing device that obtains a digital image signal by dividing an image signal of a pattern to be inspected obtained from a successive scanning two-dimensional image sensor into a mesh shape at a predetermined image division frequency. a comparator that obtains a binary signal by comparing it with a comparison level; a monostable multivibrator that generates pattern stretching pulses with long pulse widths;
The binarized signal and the pattern expansion pulse are received, the binarized signal shorter than the reference time is replaced with the pattern expansion pulse, the binary signal longer than the reference time is left as is, and the pattern is A signal emphasizing circuit for pattern processing, comprising a logic circuit that generates a signal emphasizing binary signal that is a combination of an expanded pulse and a binary signal that is longer than the reference time. 2. In the signal enhancement circuit according to claim 1,
The image signal is supplied to the plurality of comparators to extract a multi-level binary signal, and among the multi-level binary signals, the level side having more pattern features is extracted. Binarized signals for a predetermined number of levels are supplied to a combination circuit of the monostable multivibrator and the logic circuit, and the feature quantity of the signal-enhanced binary signal and the pattern obtained from the logic circuit is increased. By adding the binarized signals for the remaining levels other than the predetermined number of levels on the level side to the encoder and extracting the encoded binarized signals, one of the multi-level binarized signals A signal emphasizing circuit for pattern processing, characterized in that a binarized signal on the level side having a larger amount of pattern features is emphasized preferentially.