JPS5939782B2 - Tracer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a tracer having a plurality of memory areas and in which trigger conditions can be set independently in each memory area.

In information processing equipment, devices that retrieve operating bus information, microprogram address information, etc. at regular clock intervals and store them in memory, and later read out the stored contents to analyze the operation of the equipment, generally use tracers ( It is also called a logic analyzer) and has become indispensable for failure analysis.

Next, the conventional tracer (or analyzer) shown in Figure 1
The operation will be explained using an example of a configuration diagram. In the figure, 1 is a bus information line, 2 is a pattern comparison circuit, 3 is a pattern setting circuit, 4 is a trigger changeover switch, 5 is a trigger flip-flop, 6 is an external trigger flip-flop, 7 is a memory, 8
is an address counter, 9, 10, 11 are AND gates,
Reference numerals 12 and 13 indicate an OR gate 14 indicating a display circuit. There are three types of trigger modes, and when the trigger changeover switch 4 is switched to 1, the trigger flip-flop 5 is activated by a match signal from the pattern comparison circuit 2. 3, the trigger flip-flop 5 is activated by an external trigger signal.

When switched to 2, the trigger flip-flop 5 operates due to the arrival of both the match signal from the pattern comparison circuit and the external trigger signal.

Here, the operation when the trigger changeover switch 4 is switched to 1 will be explained.

A pattern is set in advance in the pattern setting circuit 3, and the data generated on the bus information line 1 and the pattern setting circuit 3 are
The pattern comparison circuit 2 compares the patterns, and if they match, the pattern comparison circuit 2 outputs a match signal.

This signal passes through an AND gate 9 and an OR gate 12 to set a trigger flip-flop 5, and thereafter the data on the bus information line 1 is sequentially stored in the address memory 1 indicated by the address counter 8. Note that the address counter 8 is incremented by a clock supplied from the CLK terminal. The series of data recorded in the memory T is later read out and output to the display device 14, etc., and the displayed data is referenced to perform operational analysis for failures and the like. When recording bus information, microprogram address information, etc., it is normal for the same data to occur many times, and if a trigger circuit is activated when a certain pattern appears, it will be possible to determine the point at which you want to record, such as when a failure occurs. They often don't match. In such a case, the trigger changeover switch 4 is set to 2 to set the external trigger flip-flop 6 using the fault detection signal as an external trigger signal, and then operate the trigger flip-flop 5 by the pattern matching signal generated. let In this way, it is possible to record only the operating state at the time of a failure, so that memory can be used effectively.

However, even in this case, after the trigger circuit operates, recording can only be performed within a certain memory capacity.

Figure 2 shows an example of a microprogram operation step diagram. For example, when a certain failure occurs, it is necessary to analyze the operation status of portions A, B, and C of this series of program steps. In the limited memory of a conventional tracer (or analyzer), this A, B, C
It is impossible to record so as to cover all parts of the

The purpose of the present invention is to eliminate the above-mentioned conventional drawbacks,
The example shown in Fig. 2 provides a method of omitting the operation steps between A and B and between B and C and effectively recording only the parts A, B, and C in a limited memory. It is something. The object of the present invention is to provide a tracer that continuously stores observation data in a memory upon the establishment of a certain trigger condition, and later refers to the contents recorded in the memory.
a plurality of setting means for setting trigger conditions; a plurality of memories for recording observation data corresponding to the plurality of setting means;
and recording means for recording the observation data in a memory when the trigger condition is satisfied by the setting means, and the plurality of setting means set the trigger conditions for the remaining setting means when the trigger condition is satisfied by at least one of the setting means. This is achieved by providing a gate means configured so that the following holds true.

Next, details of the present invention will be explained with reference to the drawings.

FIG. 3 shows a block diagram of a tracer (or analyzer) according to an embodiment of the present invention.

In the figure, 1 is a bus information line, 2, 15 are pattern comparison circuits, 3, 16 are pattern setting circuits, 4, 17 are trigger changeover switches, 5, 18 are trigger flip-flops, 6,
19, 27 are external trigger flip-flops, 7 is memory, 8, 21 are address counters, 9, 10, 11, 22
, 23, 24 are AND gates, 12, 13, 25, 2
6 indicates an or gate.

In this embodiment, the memory 7 is divided into two areas, page 1 and page 2, and a trigger circuit is provided independently for each page.

Therefore, for example, different patterns are set in the pattern setting circuits 3 and 16, and when the data generated on the bus information line 4 matches the pattern of the pattern setting circuit 3, the trigger flip-flop 5 is set and the subsequent Data can be recorded in page 1 of memory 7, and when it matches the pattern of pattern setting circuit 16, trigger flip-flop 18 is set and data can be recorded in page 2 of memory 7.
In this case, the time interval between the time when the trigger flip-flop 5 operates and starts recording on page 1 and the time when the trigger flip-flop 18 operates and starts recording on page 2 may be any distance. , it is possible to extract only the necessary data and effectively record it in a certain memory. Further, the operation of the trigger flip-flop 5 for page 1 is set in the trigger flip-flop 27, and the sequence is such that the operation of the trigger flip-flop 18 is operated after confirming the operation of the trigger flip-flop 5. . Therefore, since data storage for the next page 1 is performed after confirming the operation of the trigger circuit for the previous page, data that has passed through a certain route can be recorded in an orderly manner. In FIG. 3, two pattern comparison circuits and two address counters are provided for ease of understanding, but it is also possible to provide one each and use them in common.

The pattern setting circuits 3 and 16 are composed of key circuits, registers, or the like.

As described above, according to the tracer of the present invention, the memory can be divided into a plurality of areas and the trigger conditions can be independently determined in each area, so that a certain amount of memory can be used effectively.

Therefore, there is an effect of improving the efficiency of operation analysis work of an information processing device or the like using a tracer (or analyzer).

[Brief explanation of drawings]

FIG. 1 shows an example of the configuration of a conventional tracer, FIG. 2 shows an example of the operation steps of a microprogram, and FIG. 3 shows a configuration of a tracer according to an embodiment of the present invention.

Claims (1)

[Claims] 1 A tracer that continuously stores observation data in a memory when a certain trigger condition is met, and later refers to the contents recorded in the memory, and includes a plurality of setting means for setting the trigger condition, and The plurality of setting means includes a plurality of memories for recording observation data corresponding to the plurality of setting means, and a recording means for recording the observation data in the memory when a trigger condition is satisfied by the setting means, and the plurality of setting means include at least one of the plurality of setting means. A tracer comprising gate means configured such that when a trigger condition is satisfied by one setting means, a trigger condition for the remaining setting means is satisfied.