JPS5939902B2 - Complementary insulated gate field effect semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an enhancement channel complementary field effect semiconductor device whose constituent elements are metals, insulators, and semiconductors, and more specifically to a complementary field effect semiconductor device in which a gate insulating film protection device is provided within the same semiconductor substrate. It concerns field effect semiconductor devices.

In conventional field-effect semiconductor devices, which consist of metals, insulators, and semiconductors, when a high voltage is applied to the gate electrode, the insulator that electrically isolates the gate electrode and channel breaks down. The disadvantage is that it causes dielectric breakdown and permanently destroys the device.

Even if electrostatically charged clothing of a worker came into contact with the insulator while handling the device, dielectric breakdown occurred.
As a measure against dielectric breakdown of the insulator, a diode is connected between the gate electrode and the channel to prevent application of a voltage higher than the breakdown voltage of the diode to the gate electrode. In this conventional protection method, a diode is connected between the gate electrode and the channel to protect the insulator by preventing the application of a voltage higher than the breakdown voltage of the diode. If it is high, there is no effect.

In the case of actual devices, it is difficult to control the breakdown voltage of the diode to be lower than the breakdown voltage of the insulator because a substrate with a relatively low concentration is used. Therefore, the purpose of the present invention is to
To provide a field effect semiconductor device in which an excessive voltage applied to a gate electrode of an enhanced channel complementary field effect semiconductor device is reliably passed to the semiconductor substrate side before being applied to the gate electrode, thereby preventing breakdown of the gate insulating film. be.

The present invention provides a semiconductor device that further provides a complementary bipolar transistor on the semiconductor substrate on which the enhancement channel complementary field effect transistor is provided, and controls an excessive voltage applied to the gate electrode of the field effect transistor via the bipolar transistor. It is a place. Hereinafter, the structure, operation and effect of the present invention will be further explained using examples of the present invention.

1 and 2 show a top view and a longitudinal sectional view of an enhancement channel complementary field effect transistor according to the present invention.

For convenience of explanation, important parts are shown enlarged. In the figure, a SiO2 film 3 is formed on the upper surface of a rectangular N-type silicon substrate 1 provided with a P-type diffusion region 2, and a part of the film 3 is removed to form electrode extraction holes 4, 5, 6, 7, 8. ,9,10,
Drill holes 11, 12, and 13.

The electrode extraction hole has P-type diffusion regions 14, 15, 16,
17, 18, 19 and N type diffusion regions 20, 21, 22, 2
Parts of numbers 3, 24, and 25 are exposed. Further, electrode extraction holes 4, 5, 6, 7, 8, 9, 10, 11 are formed by vacuum evaporation method.
, 12, 13, and the SiQ2 coating 3 interposed between the P-type diffusion regions 14, 15 and the N-type diffusion regions 24, 25 to form electrodes 26, 27, 28, 29, 30, 31.
Configure. The P-type diffusion region 14 is a P-type source region, 15
is a P-type drain region, the N-type diffusion region 25 is an N-type source region, 24 is an N-type drain region, and the P-type drain region 1
The electrode extraction hole 5 of No. 5 and the electrode extraction hole 12 of the N-type drain region 24 are connected by a metal film electrode 28 to form a P-type and an N-type drain electrode. The P-type source region 14 and the electrode extraction hole 4 of the N-type diffusion region 20 are connected by a metal film electrode 26,
type source electrode. Further, the N-type source region 25 and the electrode extraction hole 13 of the P-type diffusion region 19 are connected by a metal film electrode 31 to form an N-type source electrode. P-type diffusion regions 17, 19
is a region to be electrically conductively connected to the P type diffusion region 2, and the N type diffusion regions 20 and 22 are respectively connected to the N type silicon substrate. The P-type diffusion region 2 of the PNP bipolar transistor, which is composed of the P-type diffusion region 2, the N-type diffusion region 23, and the P-type diffusion region 18, is the P-type collector region and the N-type diffusion region 2.
3 is an N-type base region, and the P-type diffusion region 18 is a P-type emitter region. N-type collector region, P
The type diffusion region 16 is used as a P type base region, and the N type diffusion region 21 is used as an N type emitter region. P-type source and drain region 1
The metal film on the SlO2 film 3 interposed between 4 and 15 and between the N-type source and drain regions 25 and 24 is used as a gate electrode. The gate electrode is connected to the electrode extraction hole 11 of the P-type emitter region 18 and the electrode extraction hole 6 of the N-type emitter region 21 by the metal film electrode 27 deposited at the same time as the gate electrode. The metal film electrode 27 serves as a gate electrode, an N-type emitter electrode, and a P-type emitter electrode. The metal film of the gate electrode 27 is made to overlap with a portion of the P-type source and drain regions 14 and 15 and the N-type source and drain regions 25 and 24 below the film 3 via the SiO2 film 3. The electrode extraction hole 7 of the P-type base region 16 and the electrode extraction hole 9 of the P-type diffusion region 17 are connected by a metal coating electrode 29 to form a P-type base electrode.

Further, the electrode extraction hole 10 of the N-type base region 23 and the electrode extraction hole 8 of the N-type diffusion region 22 are connected by a metal coating electrode 30 to form an N-type base electrode. The electrode of the P-type collector region 2 is an N-type source electrode 31 connected via the P-type diffusion region 19 . Further, the electrode of the N-type collector 1 is assumed to be a P-type source electrode 26 connected via an N-type diffusion region 20. Next, the protection operation of the enhancement channel complementary field effect transistor configured as described above will be explained.

A positive voltage is applied to the P-type source electrode 26 with respect to the N-type source electrode 31 .

When the voltage of the gate electrode 27 is set to zero, the N-type drain electrode 28 and the N-type source electrode 31 are electrically disconnected, and the P-type drain electrode 28 and the P-type source electrode 26 are electrically connected. In addition, the N-type emitter electrode 27 and the P-type base electrode 2
9 are at the same potential, the N-type emitter electrode 27 and the N-type collector electrode 26 of the NPN bipolar transistor are in a disconnected state, and the N-type base electrode 30 is the N-type source electrode with respect to the P-type emitter electrode 27. 31 and P-type source electrode 2
6 is applied in the opposite direction, the P-type emitter electrode 27 and the P-type collector electrode 31 of the PNP bipolar transistor are also electrically disconnected. here,
When a negative excessive voltage is applied to the gate electrode 27, the PNP
The bipolar transistor has a P type emitter electrode 27 and an N
The voltage applied in the reverse direction across the type base electrode 30 increases and the shearing state continues, but the NPN bipolar transistor
Since the voltage of the type emitter electrode 27 becomes a negative voltage, a current flows from the P type base electrode 29 to the N type emitter electrode 27, and conduction occurs between the N type collector electrode 26 and the N type emitter electrode 27. hold the voltage at zero. Next, when a positive voltage having the same potential as that between the N-type source electrode 31 and the P-type source electrode 26 is applied to the gate electrode 27, conduction occurs between the N-type drain electrode 28 and the N-type source electrode 31, and the P-type drain electrode 28 There is an electrically disconnected state between the P-type source electrode 26 and the P-type source electrode 26. Further, since the voltage between the N-type source electrode 31 and the P-type source electrode 26 is applied in the opposite direction to the P-type base electrode 29 with respect to the N-type emitter electrode 27, the N-type emitter electrode 27 of the NPN bipolar transistor and the N-type collector electrode 26 are in a disconnected state, and the P-type emitter electrode 21 and the N-type base electrode 30 are at the same potential.
The P-type emitter electrode 27 and the P-type collector electrode 31 of the NP bipolar transistor are now in a disconnected state. If an excessively positive voltage is applied to the gate electrode 27 here, NI)
The N bipolar transistor has an N type emitter electrode 27 and a P
The voltage applied in the reverse direction between the type base electrodes 29 increases and the disconnection state continues, but since the voltage of the P type emitter electrode 27 of the PNP bipolar transistor becomes a positive voltage with respect to the N type base electrode 30, the P type emitter A current flows from the electrode 27 to the N-type base electrode 30, conduction occurs between the P-type emitter electrode 27 and the P-type rectifier electrode 31, and the P-type emitter electrode 27
is maintained at the voltage between the N-type source electrode 31 and the P-type source electrode 26. As described above, the voltage of the gate electrode 27 is set to the above N
This is limited by the conduction of PN and PNP bipolar transistors.

Although the above description has been made regarding a complementary field effect semiconductor device using an N-type silicon substrate, it can also be applied to a complementary field-effect semiconductor device using a P-type silicon substrate.

The SiO2 film described above is not limited to this, and any electrical insulator may be used. The semiconductor material is not limited to silicon, and other semiconductor materials such as germanium may be used.

[Brief explanation of the drawing]

Figure 1 is a soil surface diagram of the device related to the present invention, and Figure 2 is the soil level diagram of the device related to the present invention.
FIG. 3 is a sectional view taken along the line AN in the figure, and is a circuit diagram of a device according to/alternative to the present invention. In each figure, the same reference numerals indicate the same or equivalent parts.
1 is an N-type silicon substrate, 2 is a P-type diffusion region, 3 is SiO
2 membranes, 4 to 13 electrode extraction holes, 14 to 19 P type diffusion regions, 20 to 25 N type diffusion regions, 26 to 31
is a metal coated electrode.

Claims (1)

[Claims] 1 A source region and a drain region of a second conductivity type are provided on the substrate of a first conductivity type semiconductor substrate having a second conductivity type region and an insulating layer is provided on the surface of the substrate between the source region and the drain region. a first insulated gate field effect transistor comprising a gate electrode, a source region and a drain region of a first conductivity type in the second conductivity type region, and a surface of the second conductivity type region between the source region and the drain region; A second insulated gate field effect transistor comprising a gate electrode provided through an insulating layer is provided, and the respective drain regions of the first and second insulated gate field effect transistors and the respective gate electrodes are electrically connected to each other. In a complementary insulated gate field effect semiconductor which is connected to each other, a region including a region of the first conductivity type is formed in the substrate of the first conductivity type, and a region of the first conductivity type is connected to the substrate of the first conductivity type. A bipolar transistor has a first conductivity type substrate as a collector, a first conductivity type emitter, a second conductivity type base, and a second conductivity type region as a collector. The second conductivity type region of the bipolar transistor, which is composed of a second conductivity type region and a second conductivity type region, is used as a collector, a second conductivity type emitter, and a first conductivity type emitter. The second consisting of the base of
transistors are provided, the emitters of the first conductivity type and the second conductivity type are connected to the gate electrode, and the base of the first conductivity type is connected to the substrate of the first conductivity type, and the base of the second conductivity type is connected to the substrate of the second conductivity type. A complementary insulated gate field effect semiconductor device characterized in that each region is connected to the other.