JPH025309B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, particularly to a gate protection element for preventing gate breakdown of a MOS field effect transistor (hereinafter referred to as MOS FET).

In general, the gate part of a MOS FET can be regarded as a parallel capacitor, with the gate electrode and the semiconductor substrate serving as a pair of electrodes, and the oxide film between them serving as a dielectric, due to its structure. The breakdown voltage V _M of the dielectric determines the
They have their own limits. For this reason, if an abnormal voltage due to a surge or the like is applied to the gate electrode, the gate may be destroyed, so a gate protection element for the MOS FET is required.

FIG. 1 is a circuit diagram showing a conventional MOS FET gate protection circuit. In the figure, 200 is a diode connected to prevent gate destruction, and 100 is a diode connected to prevent gate destruction.
It is a MOS FET, and the gate G of the MOS FET 100 and the anode of the diode 200 are connected to the input terminal I. By inserting the diode 200 between the input terminal I and the ground terminal E in this way, a current bypass path is created to prevent excessive voltage from being applied to the gate G of the MOS FET 100, thereby preventing gate destruction. ing. Therefore, in the conventional circuit, in order for the diode 200 to effectively prevent gate breakdown of the MOS FET 100, the breakdown voltage V _B of the diode 200 needs to be lower than the breakdown voltage V _M of the MOS FET 100.

An example of a gate protection element that achieves such a low withstand voltage _VB is a horizontal type, the cross-sectional view of which is shown in Figure 2.
There is a protection diode that shorts the emitter and base of a PNP transistor. That is,
An N ⁺ type buried isolation layer 22 and a P type semiconductor substrate 21 are provided.
A P ⁺ type buried isolation layer 23 is formed, and an N
An N type epitaxial layer 24 is formed, and an N ⁺ type buried layer 22 and a P ⁺ type buried isolation layer 23 are grown in the N type epitaxial layer 24 . Furthermore, using the surface oxide film 36 as a diffusion mask, a P ⁺ -type insulating isolation region 25 is formed by diffusion so as to be in contact with a portion of the P ⁺ -type buried isolation layer 23 grown into the N-type epitaxial layer 24 . After that, P-type regions 29 and 28 which become the collector and emitter of the PNP transistor
Then, an N ⁺ type region 32, which will become a base extraction portion, is formed by diffusion. Furthermore, the base extraction N ⁺ type region 32 and the emitter P type region 28 are connected by the metal wiring 20 through the opening in the surface oxide film 36, and this is used as the input terminal I, and the collector P type region 29 is connected to the reference potential terminal E.
Connect to. Note that the input terminal I and the reference potential terminal E correspond to those shown in FIG.

Next, the principle of operation of the protection diode shown in FIG. 2 will be explained. When a surge is applied to input terminal I, the horizontal type
The depletion layer extending from the collector P-type region 29 side of the PNP transistor reaches the emitter P-type region 28, and current flows from the input terminal I to the ground terminal E due to the punch-through phenomenon, which prevents excessive voltage from being applied to the gate. As a result, the gate electrode of the MOS FET 100 is protected. However, if the thickness of the gate oxide film becomes thin or if there are pinholes, etc., the breakdown voltage V _M of the gate structure becomes smaller, so the voltage generated by the instantaneous current flowing through the protection diode 200 will In some cases, the protective effect was not sufficient.

An object of the present invention is to obtain a semiconductor device equipped with a gate protection element that can sufficiently protect even a MOS FET having a small gate breakdown voltage _VM .

According to the present invention, a semiconductor region of one conductivity type has first and second regions of another conductivity type adjacent to each other, and a third region of one conductivity type is provided within the second region. and a semiconductor device in which the aforementioned semiconductor region and the first region are connected to each other to serve as one electrode, the third region is the other electrode, and one and the other electrodes are connected to a portion to be protected from excessive voltage. get.

Next, the present invention will be explained in more detail with reference to the drawings.

FIG. 3 is a circuit diagram showing one embodiment of the present invention. In Fig. 3, a lateral PNP transistor 40
The emitter and base of the transistor 0 are short-circuited to form a protection diode, and this short-circuit point is connected to the collector of the vertical NPN transistor 500 and the input terminal I. Further, the collector of the PNP transistor 400 is connected to the base of the NPN transistor 500, and the emitter of the NPN transistor 500 is connected to the terminal E. Input terminal I and terminal E
For example, between the gate and source of a MOS FET,
It is connected to a portion between the gate electrode and ground potential that should be protected from excessive voltage.

Next, the operation of the embodiment shown in FIG. 3 will be explained. When a surge is applied to input terminal I, the horizontal type
The depletion layer extending from the collector side of the PNP transistor 400 reaches the emitter, and current instantaneously flows from the emitter to the collector due to the punch-through phenomenon.
That is, current flows from the anode to the cathode of the diode structure. Since this current becomes the base current of the vertical NPN transistor 500, the vertical NPN transistor 500 becomes conductive and discharges the surge charge applied to the input terminal I to the terminal E. After that, when the surge voltage disappears, the voltage at the input terminal I immediately attenuates, so that the base current of the vertical NPN transistor 500 is no longer supplied, and the vertical NPN transistor 500 becomes non-conductive.

The above operation differs from the conventional circuit in that the collector current of the Darlington-connected PNP transistor 400 occurs at a very small current, about the same as the base current of the NPN transistor 500, so the corresponding punch-through voltage also occurs at a low level. Therefore, even if the gate breakdown voltage V _M of the MOS FET 300 is lowered, the gate can be reliably protected.

4a to 4c are structural cross-sectional views showing the manufacturing process of an embodiment of the present invention. Next, a step-by-step explanation will be given. First, as shown in FIG. 1A, an N ⁺ type buried region 2 and a P ⁺ type buried region 3 are formed in a P type semiconductor substrate 1 by a well-known method. Next, an N-type epitaxial layer 4 is grown on the semiconductor substrate 1 by a vapor phase growth method, and a P ⁺ -type insulating isolation region 5 is formed on the epitaxial layer 4 by a well-known method in order to create an electrically insulated region. form. At this time, the
P ⁺ -type buried region 3 also rises toward epitaxial layer 4 and is continuous with insulating isolation region 5 . Next, figure b
The epitaxial layer 4 is coated in a known manner as shown in FIG.
MOS FET300 (here P channel MOS
A P-type source region 6 and a drain region 7 of a lateral PNP transistor 400 (using a FET) and a P-type emitter region 8 and a collector region 9 of a lateral PNP transistor 400 are simultaneously formed. Thereafter, the N ⁺ type channel stopper region 10 of the MOS FET 300, the N type emitter region 11 and the N ⁺ type collector region 12 of the vertical NPN transistor 500 (the horizontal type PNP transistor 400)
(which also serves as an N ⁺ type base contact region) is formed at the same time. Subsequently, the gate G of the MOS FET 300 is formed by a well-known method. Next, as shown in FIG.
5 and 16, 17, and 18 are formed. At this time,
A protection element is formed that combines the emitter-base shorted diode D of the horizontal PNP transistor 400 and the vertical NPN transistor 500, and the anode 13 of the diode and the collector electrode 15 of the vertical NPN transistor 500 are connected to a common input. Connected to terminal I, vertical NPN transistor 50
0 emitter electrode 14 is connected to terminal E. In this way, the protection element for preventing gate breakdown according to the present invention is manufactured.

According to this embodiment of the present invention, it is possible to quickly and reliably bypass the excessive voltage applied to the input terminal I by using a new protection element, thereby preventing gate breakdown. Note that there is no new additional step in the present invention.

As described above, according to the present invention, it is possible to quickly and reliably prevent gate destruction without adding any new additional steps using conventional manufacturing methods, so it is possible to prevent gate destruction when the gate oxide film becomes thin or has pinholes, etc. It is possible to provide a gate protection element that exhibits a sufficient protective effect even if the gate breakdown voltage is lowered.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and even if the polarity is changed, the scope of the present invention does not depart from the scope of the present invention.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing a conventional MOS FET circuit, Fig. 2 is a structural cross-sectional view of a conventional diode incorporated in the circuit shown in Fig. 1, and Fig. 3 is a MOS FET according to an embodiment of the present invention. A circuit diagram showing a circuit incorporating a gate protection element of an FET, and FIGS. 4a to 4c are structural cross-sectional views showing the manufacturing process of a gate protection element according to an embodiment of the present invention. 100,300...MOS FET, G...MOS
FET gate, I...input terminal, E...ground terminal, 200,400...horizontal PNP transistor,
500...vertical NPN transistor, 1,21...
...P-type semiconductor substrate, 2,22...N-type buried region,
3, 23... P-type buried region, 4, 24... N-type epitaxial layer, 5, 25... P-type isolation region, 6... P-type source region, 7... P-type drain region, 8 ... P-type emitter region of the horizontal PNP transistor, 9 ... P-type collector region of the horizontal PNP transistor, 10 ... N ⁺ type channel stopper region, 11 ... N ⁺ of the vertical NPN transistor
type emitter region, 12... N ⁺ type collector contact region of vertical NPN transistor and N ⁺ type base contact region of horizontal PNP transistor, 13
...Emitter electrode of horizontal PNP transistor, 1
4...Emitter electrode of vertical NPN transistor,
15... Collector electrode of vertical NPN transistor and base electrode of horizontal PNP transistor, 16...
...MOS FET source electrode, 17...MOS
Drain electrode of FET, 18... Gate electrode of MOS FET, 19, 36... Surface oxide film.

Claims (1)

[Claims] 1 A unipolar type in which a semiconductor substrate of one conductivity type is used as a base region, and first and second regions of another conductivity type formed on the semiconductor substrate laterally spaced apart from each other serve as an emitter region and a collector region, respectively. a lateral transistor, and a third region of one conductivity type formed in the second region is an emitter region, and the second region is an emitter region.
a vertical transistor of another polarity type in which the region is a base region and the semiconductor substrate is a collector region, and the semiconductor substrate and the first region are connected to each other and used as one electrode, and the third region is used as one electrode. A semiconductor device characterized in that the one and the other electrodes are connected as the other electrode to a portion to be protected from excessive voltage.