JPS5940349B2 - TV receiver small screen storage method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for storing a small screen of a television receiver, a so-called picture-in-picture receiver, which can project a small screen of another channel on the television screen using its own device. It was developed for the purpose of writing the entire text so that subtitles on small screens would not be cut off, as was the case in the past.

First, the conventional small screen storage method will be explained based on the first time chart. SB in the figure is a small screen signal for small screen video formed by the receiver, and this signal is sent out sequentially, for example, to the first field fl, second field f2, third field f3, etc. be done. WT is a writing period signal of the small screen signal SB, and this signal is, for example,
In period W1, the small screen signal SB of only the central portion of the first field f0 excluding both end portions is sampled and written into memory A of a pair of memories (not shown), and similarly, in period W2, The small screen signal SB at the center of the second field f2 is sampled and written into the B memory, the other of the pair of memories (not shown). RD is a readout period signal of the small screen signal SB, and this signal, for example, reads out the center portion of the first field f of the small screen signal SB written in the memory A in period C, with an earlier period. Similarly, in period D, the central portion of the second field f2 of the small screen signal SB written in the B memory is read out with an earlier period. In the conventional small screen storage method described above, for example, in the case of the A memory, the central portion of the first field fl of the small screen signal SB is written in the period W1 of the write period signal WT, and then this first field fl is written.
The central part of the field fl is read out during the period C of the read period signal RD, and then the third field f3 is read out during the period C of the read period signal RD.
The central portion of is written again in the period W3 of the write period signal WT. However, in the case of this small screen storage method, X during the writing period W, , W2, W3...
Read periods A, B, C... Since the beams are set large, for example, although the end of period C does not overlap with the start of period W3, write periods W, W2, W3
. . . could not be made larger than a certain level, and there was a problem that the scores of sports programs, time display, etc. were partially missing.

The present invention solves the above-mentioned problems, and first, an embodiment will be described based on FIG. 1.

WTE in the figure is the write period signal of the small screen signal SB,
This signal is e.g.
The small screen signal SB from the middle to the end excluding the starting edge f, , and the starting edge F2l of the second field F2 excluding the vertical retrace period V2 is stored in one memory A of the pair of memories, which will be described later. Write while sampling, and in period β, the second
to the end of the field F2 excluding the starting point F2l, and the starting point F of the third field F3 excluding the vertical retrace period V,
The small screen signal SB of 3l is sampled and written into the other B memory (not shown) of the pair of memories. After this, for example, during the period C during which the small screen signal SB written in the A memory in the period α is read out from the A memory, that is, during the period β−C, the second field F
2, the tip F2l is the first field F, and the rear end Fl2
When reading the contents of the section C'(:A memory, first read the tip F of the second field F2.
2, and then the rear end portion F, 2 of the first field F, is read out. Similarly, during the period D when the small screen signal SB written in the B memory during the period β is read out from the B memory, that is, during the period γ-D,
Operate so that the tip F3l of the third field F is in front of the rear end F22 of the second field F2, and
(When reading out the contents of the 'B memory, first read out the tips F and l of the third field F, and then read out the rear end F22 of the second field F2.Specifically, illustrations are omitted. When a random access memory RAM is used for the pair of memories, for example, the number of bits written in the rear end Fl2 of the first field f1 is counted in advance, and this count is applied to the address counter. If input to the preset, when reading from the random access memory, first the tip F of the second field F2 is input.
2l is read out, and then the first field f
The rear end F, 2 of 1 will be read out.

When using a shift register in a pair of memories (not shown), for example, after writing the rear end Fl2 of the first field F and the start end F2l of the second field F2, the output and input of the shift register are If the rear end Fl2 of the first field f1 is read out once after combining, the rear end Fl2 of the first field F will be written again after the leading end F2 of the second field F2. Therefore, when reading from the shift register, first the leading end F2 of the second field F2 is read out, and then the succeeding part Fl2 of the first field f1 is read out. In the present invention as described above, after writing the small screen signal SB to the memory, it is possible to write the entire video signal of the small screen to the memory by exchanging the data or changing the address. This eliminates problems such as subtitles being cut off around small screens.

Note that here, the random access memory R is used as the pair of memories.
The case where AM is used will be explained based on the block diagram of FIG.

In the figure, MAIN/V is the main vertical synchronization signal obtained from the main screen signal for main screen video, MAIN/A1 is the main horizontal synchronization signal obtained from the main screen signal as above, and 21 is the vertical readout by inputting these signals. A signal forming circuit 22 outputs a readout period signal RD of the small screen signal SB, an oscillation circuit 23 generates a clock signal READCK for horizontal reading of the small screen signal SB. , a signal forming circuit for outputting to a memory (not shown), which receives the read period signal RD and the read clock signal from the oscillation circuit 22, respectively.

SUB/H is a sub-horizontal synchronization signal obtained from the small-screen signal SB for small-screen video, and 24 is a sub-horizontal synchronization signal obtained from the small-screen signal SB for small-screen video. 24 manually inputs this signal and the readout period signal RD, and vertical writing is possible using the trailing edge of the signal RD. This is a signal shaping circuit that outputs a signal, that is, a write period signal WTE of the small screen signal SB.

Note that this circuit outputs numerical information of the sub-horizontal synchronizing signal SUB/H, that is, information HN about the number of scans. 25 is an oscillation circuit that generates a write clock signal for the small screen signal SB; 26 is a signal forming circuit that outputs a clock signal WRlTECK that enables horizontal writing of the small screen signal SB to a memory (not shown); The period signal WTE and the write clock signal from the oscillation circuit 25 are respectively input.

27 is a head pointer which is a counter for presetting, and this pointer inputs the information HN of the number of scans counted by the signal forming circuit 24 and outputs the information obtained from the small screen signal SB for small screen video to the code terminal LD. When the sub vertical synchronizing signal SUB/V is input, information HN of the number of scans counted up to that time is loaded.

For example, during the period α in FIG. The number of scans written in the first month of the abbreviated A memo is stored and held, and this number of scans is output to the head address generator 281 at the subsequent stage. The head address generator 28 generates the number of scans held in the head pointer 2r, for example, the rear end F of the first field f1 in FIG.
The address preset signal ADP corresponding to l2 is outputted and preset inputted to the address counter 29 at the subsequent stage. The address counter 29 receives a horizontal readable clock signal READCK and a horizontally writable clock signal WRITECK. Thus, when writing the small screen signal SB to the random access A memory (not shown) during the writing period α in FIG. With address signal WADDRE for writing/reading, first, the trailing end Fl2 of the first field f1, and then the starting end F2l of the second field F2.
are written respectively. When reading the contents written from this A memory, address counter 2 must be read.
9 is preset by the address preset signal ADP from the head address generator 28 during the period β-C in FIG. Then, the start end F2l of the second field F2 is first read out during the readout period C in FIG. The rear end Fl2 of the first field FO will be read out.

Furthermore, a case where a shift register is used for a pair of memories will be explained based on the block diagram of FIG.

31 in the figure is a signal forming circuit that inputs the main vertical synchronizing signal MAlN/V and the main horizontal synchronizing signal MAlN/4-1 and outputs the vertical read enable signal, that is, the read period signal RD of the small screen signal SB. , 32 is an oscillation circuit that generates a readout clock signal for the small screen signal SB;
Reference numeral 3 denotes a signal forming circuit that outputs a horizontally readable clock signal READCK of the small screen signal SB to a memory (not shown). input.

Note that PG is a gate signal for controlling the small screen interruption to the main screen, and this signal inputs the read period signal RD and the signal from the signal forming circuit 33 to the AND gate 35, respectively. Obtained by. 36 inputs the sub-horizontal synchronizing signal SUB/11 and the read period signal RD, and uses the trailing edge of the signal RD to generate the vertical write enable signal, that is, the write period signal W of the small screen signal SB.
This is a signal forming circuit that outputs TE.

Note that this circuit outputs numerical information of the sub-horizontal synchronizing signal SUB/H, that is, information HN about the number of scans. 3r is an oscillation circuit that generates a write clock signal of the small screen signal SB, and 38 is a signal forming circuit that outputs a horizontally writable clock signal WRlTECK of the small screen signal SB to a memory (not shown). The write clock signals from the WTE and the oscillation circuit 3r are respectively input.

39 is a head pointer which is an up-down counter for presetting, and this pointer inputs the information HN of the number of scans counted by the signal forming circuit 36, and when the sub vertical synchronizing signal SUB/V is input to the load terminal LD. Then, the information HN of the number of scans counted up to that time is loaded, and when the memory contents are rotated (this power is reduced).

For example, during the period α in FIG. The number of scans written in the memory is stored and held, and the output of the array restrictor 40 at the subsequent stage is detected to subtract this number of scans.
Note that the head pointer 39 is connected to the main horizontal synchronizing signal MA.
IN/H is used as a synchronizing signal for subtraction counting, and a signal for rotating the contents of a memory (not shown) is output to the OR gate 34. The array Illll controller 40 rotates the contents of the small screen signal SD written in a memory (not shown) and controls the number thereof, and when the main vertical synchronization signal MAIVV is input, the head pointer 39 The contents in memory A are rotated by the number of scans loaded in memory A.

For example, in the write period α, first the trailing edge Fl2 of the first field F and then the starting edge F2l of the second field F2 are written in memory A, and as a result, the number of scans is only the rear end Fl2 of the first field F is connected to the second field F2.
Perform a rotational movement operation after the starting points F and l. Thus, when writing the small screen signal SB to the A memory of the shift register (not shown) during the writing period α in FIG. The trailing end F, 2 of the field f1, and then the starting end F2l of the second field F2 are written respectively. When reading the written content from memory A, the content in memory A has already been rotated, for example, during period β-C in FIG.
With EADCK, for example, the read period C in FIG.
First, the starting end F2 of the second field F2 is read out, and then the trailing end F2 of the first field F2 is read out.

[Brief explanation of drawings]

Figure 1 is a time chart explaining the method of the present invention;
The figure is a block diagram of one embodiment embodying FIG. 1, and FIG. 3 is a block diagram showing another embodiment. SB: Small screen signal, rear end of Fl2/F22/F322 field, Fll. f2,, f3,: Field tip.

Claims (1)

[Claims] 1. In a television receiver capable of projecting a small screen on the TV screen, the rear end of a field with a small screen signal for small screen reception and the leading end of the next field are stored in sequence, and these small screen signals are then read out. When reading out the stored small screen signal by operating so that the leading edge of the next field comes before the trailing edge of the certain field, the leading edge of the next field is read out first; A small screen storage method for a television receiver, characterized in that the rear end of the certain field is then read out.