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JPS594075B2 - Pattern Kensa Sochi - Google Patents
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JPS594075B2 - Pattern Kensa Sochi - Google Patents

Pattern Kensa Sochi

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Publication number
JPS594075B2
JPS594075B2 JP50153100A JP15310075A JPS594075B2 JP S594075 B2 JPS594075 B2 JP S594075B2 JP 50153100 A JP50153100 A JP 50153100A JP 15310075 A JP15310075 A JP 15310075A JP S594075 B2 JPS594075 B2 JP S594075B2
Authority
JP
Japan
Prior art keywords
signal
inspected
pattern
width
pattern body
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP50153100A
Other languages
Japanese (ja)
Other versions
JPS5273057A (en
Inventor
巌 原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kubota Corp
Original Assignee
Kubota Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kubota Corp filed Critical Kubota Corp
Priority to JP50153100A priority Critical patent/JPS594075B2/en
Publication of JPS5273057A publication Critical patent/JPS5273057A/en
Publication of JPS594075B2 publication Critical patent/JPS594075B2/en
Expired legal-status Critical Current

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  • Measurement Of Length, Angles, Or The Like Using Electric Or Magnetic Means (AREA)
  • Length Measuring Devices By Optical Means (AREA)
  • Inspection Of Paper Currency And Valuable Securities (AREA)

Description

【発明の詳細な説明】 本発明は、紙幣などシート状の被検査パターン体があら
かじめ設定された真正パターンの巾ならびに長さと一致
するか否かによつて、当該被検査5 パターン体を検査
する装置に係り、該パターン検査装置の構成を改良して
比較的少ない検知器群により被検査パターン体の送り速
度などに関係なく、当該被検査パターン体を正確に判別
しようとする目的から開発されたものである。
[Detailed Description of the Invention] The present invention inspects five pattern bodies to be inspected, depending on whether the sheet-like pattern body to be inspected, such as a banknote, matches the width and length of a preset authentic pattern. This system was developed for the purpose of improving the configuration of the pattern inspection device and using a relatively small group of detectors to accurately discriminate the pattern object to be inspected, regardless of the feed speed of the pattern object. It is something.

10まず、実施例を添付図面にもとづき説明すると、P
iは1000円紙幣など一定の巾Wと一定の長さdとを
有する被検査パターン体、1はこの被検査パターン体を
通過せしむ通路ケースで、該通路ケースは被検査パター
ン体Piを挿入する挿入口152ならびに排出する排出
口3を有している。
10 First, the embodiment will be explained based on the attached drawings.
i is a pattern body to be inspected having a constant width W and a constant length d, such as a 1000 yen bill; 1 is a passage case through which this pattern body to be inspected passes; the passage case inserts the pattern body Pi to be inspected. It has an insertion port 152 for discharging and an ejection port 3 for discharging.

D1は通路ケース1の挿入口2寄りに設けられる被検査
パターン体Piの挿入確認用の検出器群で、該挿入確認
用検出器は光源ならびに受光素子あるいは磁気検出素子
などからなり、被検査パタク0−ン体Piの挿入口2へ
の投入を検出して、当該被検査パターン体を通路ケース
1内にさらに引き込む装置(図示省略)を作動する。D
el、De2は通路ケース1の中央寄りに設けられる被
検査パターン体Piの一方、他方サイドを25検出する
エッジ検出器で、該エッジ検出器は被検査パターン体P
iのサイドにおけるパターンに対応した信号を発し、光
源ならびに受光素子あるいは磁気検出素子などからなり
、通路ケース1内を移動する被検査パターン体P1の両
エッヂを検出30して、第2図、第3図の如く、両検出
信号の和であるエッジ検出信号eを出力する。
Reference numeral D1 denotes a group of detectors for checking the insertion of the pattern to be inspected Pi, which is provided near the insertion opening 2 of the passage case 1. A device (not shown) is actuated to detect the insertion of the pattern body Pi into the insertion port 2 and draw the pattern body to be inspected further into the passage case 1. D
el and De2 are edge detectors for detecting one side and the other side of the pattern body Pi to be inspected, which are provided near the center of the passage case 1;
A signal corresponding to the pattern on the side of i is emitted, and both edges of the pattern body P1 to be inspected, which is composed of a light source, a light receiving element or a magnetic detecting element, etc. and moves within the passage case 1, are detected 30, and as shown in FIG. As shown in FIG. 3, an edge detection signal e, which is the sum of both detection signals, is output.

第2図のDAは差動(比較)増巾器で、該差動増巾器は
エッジ検出信号e)ならびに被検査パターン体Piの真
正パターン体の巾にもとづきあら35かじめ設定された
真正信号twをそれぞれ入力比較して巾検査信号iを出
力する。
DA in FIG. 2 is a differential (comparison) amplifier, and the differential amplifier is used to detect the edge detection signal e) and the width of the genuine pattern body of the pattern body Pi to be inspected. The signals tw are inputted and compared, and a width inspection signal i is output.

言い換えると、エッジ検出信号eが真正巾信号twより
も大きけれ1ηハば、エツジ検出器Del,De2の両
方が被検査パターンPiを検出していることになるから
、巾検査信号1が低レベルになるか否かにようて被検査
パターン体Piの巾wが真正パターンの巾と同一である
か否かを検査できることになる。
In other words, if the edge detection signal e is larger than the true width signal tw by 1η, both the edge detectors Del and De2 are detecting the pattern to be inspected Pi, so the width inspection signal 1 becomes low level. Depending on whether or not the width w of the pattern body Pi to be inspected is the same as the width of the genuine pattern, it can be inspected.

TSは差動増巾器DAの後段に設けられるイキ値判別器
で、該イキ値判別器は一対の比較器CMl,CM2など
からなり巾検査信号1を入力して、該検査信号があらか
じめ設定されるイキ値巾hを越えると高レベルとなり、
イキ値巾h内にあれば、低レベルとなるパルス信号Pを
出力する。Gはイキ値判別器TSの後段に設けられるナ
ンドゲートで、該ゲートはパルス信号Pを入力すると共
に、被検査パターン体Piの通路ケース1内への引き込
み速度すなわち送り速度に同期したパルス列信号Pdを
入力してパルス信号Pが低レベルであるときにパルス列
信号Pdを通過させ、検査パルス信号w&dを出力する
。CTはナンドゲートGの後段に設けられるカウンタで
、該カウンタは検査パルス信号w&dを入力して計数し
計数信号αを出力する。
TS is a prime value discriminator installed after the differential amplifier DA, and the prime value discriminator is composed of a pair of comparators CMl, CM2, etc., and inputs the width test signal 1, so that the test signal is set in advance. When it exceeds the orgasm value range h, it becomes a high level,
If it is within the peak value width h, a pulse signal P having a low level is output. G is a NAND gate provided after the live value discriminator TS, which inputs the pulse signal P and also receives the pulse train signal Pd synchronized with the drawing speed, that is, the feeding speed of the pattern body Pi to be inspected into the passage case 1. When the input pulse signal P is at a low level, the pulse train signal Pd is passed through and the test pulse signal w&d is output. CT is a counter provided after the NAND gate G, and this counter inputs the test pulse signals w&d, counts them, and outputs a count signal α.

なお、RはカウンタCTをりセツトする信号で、該信号
は、たとえば被検出パターン体Piが通路ケース1内に
挿入されて検出器Diにより検出されたときなどのスタ
ート時に印加される。PSは設定器で、該設定器は被検
出パターン体Piの真正パターン体にもとづく真正計数
信号βを出力する。G1はカウンタCTの後段に接続さ
れるアンドゲートで、該ゲートは計数信号αならびに真
正計数信号βをそれぞれ入カチエツクして、当該計数信
号αが真正計数信号βと一致するときのみ、真正信号w
′0Cd′を出力する。第3図波形図について説明する
と、Del,De2のエツジ検出器出力eは第3図e及
びiの波形のようであり左側が正常検出パターンで右側
が異常(黒いもの)検出パターンの波形である。
Note that R is a signal for resetting the counter CT, and this signal is applied at the start, such as when the detected pattern body Pi is inserted into the passage case 1 and detected by the detector Di. PS is a setting device, and the setting device outputs a genuine count signal β based on the genuine pattern body of the detected pattern body Pi. G1 is an AND gate connected after the counter CT, which gate inputs the count signal α and the true count signal β, and outputs the true signal w only when the count signal α matches the true count signal β.
Output '0Cd'. To explain the waveform diagram in Figure 3, the edge detector output e of Del and De2 is like the waveforms in Figure 3 e and i, where the left side is the normal detection pattern and the right side is the waveform of the abnormal (black) detection pattern. .

RIuhは次段のイキ値判別の巾である。各出力はP波
形のようにイキ値判別回路で作られる。被検出パターン
の送り速度に同期したパルスPd波形図の様であり、P
.ll!l:Pdの同期によりCT回路に計数カウント
される。被検出パターンが送り込まれて停止するとw〜
d′の出力が第3図w′0Cd′波形のように左側は出
力されるが、右側では出力されない。
RIuh is the width for determining the next stage's vitality value. Each output, like the P waveform, is generated by a peak value discrimination circuit. It looks like a pulse Pd waveform diagram synchronized with the feed speed of the detected pattern, and P
.. ll! 1: Counted by the CT circuit by synchronization of Pd. When the detected pattern is sent and stopped lol
The output of d' is output on the left side as shown in the waveform w'0Cd' in FIG. 3, but not on the right side.

上記の如くなる本発明は、1000円紙幣などの被検査
パターン体Piを通路ケース1の挿入口2内に投入する
と、該被検査パターン体Piが検出器Diによつて検出
され、図示省略の引き込み装置により当該被検査パター
ン体Piが通路ケース1内にさらに引き込まれると共に
、検出器Del,De2群によつて移動する該被検査パ
ターン体の両サイド部が検出されてエツジ検出信号eが
出力されることになる。
In the present invention as described above, when a pattern body Pi to be inspected, such as a 1000 yen bill, is inserted into the insertion opening 2 of the passage case 1, the pattern body Pi to be inspected is detected by the detector Di. The drawing device further draws the pattern body Pi to be inspected into the passage case 1, and the detectors Del and De2 group detect both sides of the pattern body to be inspected, and an edge detection signal e is output. will be done.

かくして、あらかじめ設定された真正巾信号Twを入力
する差動増巾器DAを介してエツジ検出信号eが比較検
査され、被検査パターン体Piの巾wが真正パターンの
巾と同一であることを意味する巾検査信号1が当該差動
増巾器DAから出力されると共に、イキ値判別器TSを
介在してパルス信号Pが出力される。
In this way, the edge detection signal e is comparatively inspected via the differential amplifier DA which inputs the true width signal Tw set in advance, and it is confirmed that the width w of the pattern body Pi to be inspected is the same as the width of the true pattern. A width test signal 1 is outputted from the differential amplifier DA, and a pulse signal P is outputted via the peak value discriminator TS.

つぎに、被検査パターン体Piの送り速度に同期された
パルス列信号Pd及びパルス信号Pを入力するナンドゲ
ートGを介してパルス信号Pが低レベルであるとき(幅
検出信号がイキ値h内にあるとき)のみパルス列信号P
dを検査パルス信号w&dとして通過させる。
Next, when the pulse signal P is at a low level (the width detection signal is within the current value ) only when the pulse train signal P
d is passed as the test pulse signal w&d.

該検査パルス信号w&dは、カウンタCTで計数され、
該カウンタCTの計数信号αが被検査パターン体Piの
真正パターンの長″さに対応する真正計数信号βと一致
すると、アンドゲートG1から真正信号w′&D7を出
力し、被検査パターンを真とみなし、逆に真正信号1&
d勺{発せられず、被検査パターンを偽とみなして、被
検査パターン体Plの巾wならびに長さdが検査される
ことになる。以上の如くなる本発明は、被検出パターン
の両サイドを検出する一対のエツジ検出器に基づく工ツ
ジ検出信号と、真正パターンの巾に対応する真正巾信号
とを差動比較した幅検出信号が予め設定されたイキ値に
あるか否かによつて被検査パターン体の幅を検査し、こ
の幅検出信号がイキ値内にあるときのみ被検査パターン
体の送り速度に同期したパルス列信号を検査パルス信号
として出力させ、該検査パルス信号を計数するカウンタ
の計数するカウンタの計数信号が被検査パターン体の真
正パターン体の真正パターンの長さ基づく真正計数信号
に等しいときに真正信号を発し、被検査パターン体の長
さを検査しているから、検出器群を2個と比較的少ない
数にすることができると共に、被検査パターン体Plの
移動速度に関係なく、当該被検査パターン体Piの巾w
ならびに長さdを正確に検査できることになるなど、実
用上の効果大なるものがある。
The test pulse signals w&d are counted by a counter CT,
When the count signal α of the counter CT matches the true count signal β corresponding to the length of the true pattern of the pattern body Pi to be inspected, the AND gate G1 outputs the true signal w'&D7, and the pattern to be inspected is determined to be true. Deemed, conversely true signal 1&
d is not emitted, the pattern to be inspected is regarded as false, and the width w and length d of the pattern to be inspected Pl are inspected. In the present invention as described above, a width detection signal is obtained by differentially comparing an edge detection signal based on a pair of edge detectors that detect both sides of a pattern to be detected and an authentic width signal corresponding to the width of an authentic pattern. The width of the pattern object to be inspected is inspected depending on whether it is within the preset value, and only when this width detection signal is within the limit value, the pulse train signal synchronized with the feed speed of the pattern object to be inspected is inspected. When the count signal of the counter that counts the test pulse signal is equal to the genuine count signal based on the length of the genuine pattern of the genuine pattern body of the pattern body to be inspected, the genuine signal is outputted. Since the length of the inspection pattern body is inspected, the number of detector groups can be reduced to two, which is relatively small, and the length of the inspection pattern body Pi can be adjusted regardless of the moving speed of the inspection pattern body Pl. Width lol
In addition, it has great practical effects, such as being able to accurately inspect the length d.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の実施例要部をしめす略示的な平面図、
第2図は同上実施例の配線図、第3図は動作波形図であ
る。 Pi・・・・・・被検査パターン体、Del,De2・
・・・・・検出器、DA・・・・・・室動(比較)増巾
器、TS・・・・・・イキ値判別器、G・・・・・・ナ
ンドゲート、Tw・・・・・・真正巾信号、Pd・・・
・・・真正長さパルス信号、w・・・・・巾、d・・・
・・・長さ 。
FIG. 1 is a schematic plan view showing the main parts of an embodiment of the present invention;
FIG. 2 is a wiring diagram of the same embodiment, and FIG. 3 is an operating waveform diagram. Pi... Pattern body to be inspected, Del, De2.
...Detector, DA...Chamber motion (comparison) amplifier, TS...Iki value discriminator, G...Nand gate, Tw...・・True width signal, Pd・・
...true length pulse signal, w...width, d...
···length .

Claims (1)

【特許請求の範囲】[Claims] 1 移動する被検査パターン体の一方及び他方サイドを
検出する一対のエッジ検出器と、該検出器の検出信号の
和であるエッジ検出信号と被検査パターン体の真正パタ
ーン体の巾に基づき予め設定された真正巾信号とを差動
増巾して巾検出信号を出力する増巾器と、該増巾器から
の巾検出信号を予め設定されたイキ値にて判別してパル
ス信号に変換するイキ値判別器と、該イキ値判別器から
巾検出信号が上記イキ値にあることを示す信号が発せら
れているときのみ、上記被検査パターン体の送り速度に
同期されたパルス列信号を検査パルス信号として出力さ
せるゲートと、該ゲートからの検査パルス信号を計数す
るカウンタと、該カウンタの計数信号が被検査パターン
体の真正パターンの長さに基づく真正計数信号に等しい
ときのみ真正信号を発するゲートとからなり、上記被検
査パターン体の巾ならびに長さを検査するようにしたこ
とを特徴とするパターン検査装置。
1 A pair of edge detectors that detect one side and the other side of a moving pattern body to be inspected, an edge detection signal that is the sum of the detection signals of the detectors, and an edge detection signal that is preset based on the width of the true pattern body of the pattern body to be inspected. an amplifier that differentially amplifies the true width signal and outputs a width detection signal, and a width detection signal from the amplifier that is determined by a preset value and converted into a pulse signal. Only when a signal indicating that the width detection signal is at the above-mentioned peak value is emitted from the peak value discriminator and the peak value discriminator, a pulse train signal synchronized with the feed speed of the pattern body to be inspected is sent as a test pulse. A gate that outputs a signal, a counter that counts the inspection pulse signal from the gate, and a gate that emits an authentic signal only when the count signal of the counter is equal to an authentic count signal based on the length of the authentic pattern of the pattern body to be inspected. 1. A pattern inspection device, characterized in that the width and length of the pattern body to be inspected are inspected.
JP50153100A 1975-12-15 1975-12-15 Pattern Kensa Sochi Expired JPS594075B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50153100A JPS594075B2 (en) 1975-12-15 1975-12-15 Pattern Kensa Sochi

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50153100A JPS594075B2 (en) 1975-12-15 1975-12-15 Pattern Kensa Sochi

Publications (2)

Publication Number Publication Date
JPS5273057A JPS5273057A (en) 1977-06-18
JPS594075B2 true JPS594075B2 (en) 1984-01-27

Family

ID=15554963

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50153100A Expired JPS594075B2 (en) 1975-12-15 1975-12-15 Pattern Kensa Sochi

Country Status (1)

Country Link
JP (1) JPS594075B2 (en)

Also Published As

Publication number Publication date
JPS5273057A (en) 1977-06-18

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