JPS5941322B2 - RS flip-flop circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention utilizes integrated injection logic.
ogic) (hereinafter abbreviated as IIL)
The present invention relates to an S flip-flora circuit, and particularly to an RSS flip-flora circuit that can obtain sufficiently waveform-shaped Q and Q outputs for low-speed set 3 and reset B inputs.

Now, to briefly explain what IIL is, this logic circuit uses complementary transistors as the load of a switch circuit, for example.For convenience of explanation, the inverter gate circuit of IIL is shown in Figures 1 and 2. It is shown and explained in the figure.

In FIG. 1, T1 is an injection current supply transistor, T2 is an output transistor having a multi-collector output, IT is an injection terminal, E is ground, IN is an input terminal, and 0UT1 and 0UT2 are output terminals.

In a circuit with such a configuration, the output transistor T2
Since the base current of is supplied as a constant current from the injection terminal IT through the transistor T1, this inverter gate is connected to the inverter gate G1 consisting of the output transistor T2 and the constant current source C, as shown in FIG.
It can be expressed as

In FIG. 2, the same reference numerals as in FIG. 1 indicate phase-resonating parts.

Note that the output of the output transistor T2 was set to two terminals, but
This has no meaning.

An example of the conventional IIL RSS flip-flop circuit and input/output circuit is shown in FIG. The inputs of the inverter gate G4 are connected to each other, and the input of the inverter gate G4 is set to the set power S, and the other output is set to the Q output.

Further, the input of the inverter gate G5 is the reset human power R, and the other output is the Q output.

And G2. G3 is an inverter gate that forms the RSS flip Flora circuit input circuit, and its inputs are set human power S and reset human power R, and its output is R.
It is connected to the set human power S and reset human power R of the SS flip Flora circuit.

In addition, inverter gate G6. G7 serves as a load for the RSS flip-flop circuit, and its respective inputs are connected to the Q output and the Q output.

Next, the operation of the circuit shown in FIG. 3 will be explained with reference to the time chart of FIG. 4.

In Figure 4, V s, VR, VB, VR, VQ
The waveforms of yVQ are as follows: human power S to set inverter gate G2, human power R to reset inverter gate G3, human power S1 to set inverter gate G4, human power R to reset inverter gate G5, and inverter gate G in FIG. 3, respectively.
4 and the voltage waveform at the Q output of inverter gate G5.

First, in the initial state, Vs, VR5VR, and VQ are ゝゝL
"(approximately OV), and VB and VQ are "H" (approximately 0.7V).
).

After this, when VS rises at a very low speed, vl begins to fall little by little when the height of the voltage waveform approaches the threshold level of inverter gate G2.

Then, vH and VQ begin to rise when 100 becomes close to the threshold level of inverter gate G4.

Next, when the v hill reaches the threshold level of the inverter gate G5, VS and VQ instantly become "L" due to the positive feedback operation of the latch circuit, and VB yVQ becomes "H".
"become.

The normal operation of such a latch circuit is generally well known, and since this circuit is symmetrical when viewed from the set human power S and the reset human power R, the explanation of the operation will not end here. , a detailed explanation thereof will be omitted.

As is clear from the time chart in Fig. 4, in the conventional circuit, when the input waveforms of the set human power S and the reset human power R are slow, the output waveforms of the outputs Q and Q have a steep waveform at the rise. I can't do it.

In addition, such low-speed signals tend to cause abnormal oscillation at the threshold level of each inverter (,
When oscillating, there is a drawback that an oscillation waveform appears at the rising edge of the VQ, v, waveform.

In view of the above points, the present invention has been made to solve such problems and eliminate such drawbacks.The purpose of the present invention is to reduce the speed of the signal waveforms input to the set input and reset input by using a simple circuit configuration. However, it is an object of the present invention to provide an RSS flip-flop circuit that can obtain stable waveform-shaped Q and Q outputs.

In order to achieve such an object, the present invention provides a first and a second inverter gate having two outputs each, the first output of the first inverter gate being connected to the second inverter gate. is supplied to the input of the inverter gate, and the first output of the second inverter gate is supplied to the input of the first inverter gate.
is supplied to the input of the inverter gate of the first inverter gate, the input of the first inverter gate is set as S input, the input of the second inverter gate is set as the reset R input, and The output is Q output, the second and subsequent outputs of the second inverter gate are Q, and the suction momme current density of the second and subsequent outputs is clear with respect to the first output of the first and second inverter gates. A load inverter gate is connected to the above-mentioned Q and Q outputs so that the output voltage becomes smaller.

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 5 is a circuit diagram showing an embodiment of the RSS flip-flop circuit according to the present invention.

In FIG. 5, the same reference numerals as in FIG. 3 indicate corresponding parts, and the difference from FIG. 3 is that the inverter gate G4. In G5, the output of the Q output is twice that of the other output, and the sink current density is expressed as %.

Then, between two inverter gates having two or more outputs, the first output of one inverter gate G4 is supplied to the input of the other inverter gate G5, and the first output of the other inverter gate G5 is supplied to the input of the other inverter gate G5. is supplied to the input of inverter gate G4, and one inverter gate G4
The input of the inverter gate G5 is set as the set S input, the input of the other inverter gate G5 is set as the reset R input, the second and subsequent outputs of one inverter gate G4 are set as the Q output, and the second and subsequent outputs of the other inverter gate G5 are set as the Q output. With 4 outputs,
For the first output of inverter gates G4 and G5,
A load inverter gate G6. G7 is connected.

Next, the operation of the embodiment shown in FIG. 5 will be explained with reference to the time chart of FIG. 6.

Note that each symbol in FIG. 6 is the same as in FIG. 4.

The initial state is also the same as that shown in FIG.

First, Vs rises at a very low speed (then, when its height approaches the threshold level of inverter game 1-G2, vH begins to fall little by little).

Then, when Vs approaches the threshold level of inverter gate G4, the V hill begins to rise.

However, VQ still remains at "L".

This is because, among the outputs of the inverter gate G4, the sink current density of the Q output is % of the output connected to the reset human power R.

Next, when VR reaches the threshold level of inverter gate G5, VS and VQ instantly become L" due to the positive feedback operation of the latch circuit, and Vi and vQ become H".

Furthermore, due to the symmetry of this circuit, the operation can be followed in the same way for a low-speed signal from the reset input R.

That is, the waveforms of VQ and Vi have steep rises and falls regardless of the slow input waveforms, and are not affected even if abnormal oscillation occurs.

As is clear from the above description, according to the present invention, the sink current density of the second and subsequent outputs is clearly smaller than the first output of the first and second inverter gates without using complicated means. With a simple circuit configuration in which a load inverter gate is connected to the Q and Q outputs so that Since the circuit can be realized, the practical effect is extremely good.

[Brief explanation of drawings]

Figures 1 and 2 are circuit diagrams for explaining the IIL inverter gate circuit, Figure 3 is a circuit diagram for explaining an example of a conventional RSS flip-flop circuit, and Figure 4 is a time chart for explaining the operation of Figure 3. , FIG. 5 shows the RSS according to the present invention.
FIG. 6 is a circuit diagram showing one embodiment of the flip-flora circuit, and FIG. 6 is a time chart for explaining the operation of FIG. 5. T1: Injection current supply transistor, T2: Output transistor with multi-collector, C: Constant current source, G1 to G7.
...IIL inverter gate, S...set input, R...reset input, Q...
・Q output, Q...Q output.

Claims (1)

[Claims] 1. In an inch-grated injection logic circuit, between two inverters, first and second, each having at least two outputs, a first output of the first inverter gate is connected to a first output of the second inverter gate. a first output of the second inverter gate is supplied to the input of the first inverter gate, and sets the input of the first inverter gate S
input, the input of the second inverter gate is an R input, and the second input of the first inverter gate is
The subsequent output is defined as Q output, the second and subsequent outputs of the second inverter gate are defined as q output, and the sink current density of the second and subsequent outputs with respect to the first output of the first and second inverter gates is An RSS flip-flop circuit characterized in that a load inverter gate is connected to the Q and Q outputs so as to be clearly small.