JPS5941556B2 - digital rate measuring device - Google Patents

Description

[Detailed description of the invention] The present invention relates to improvements in rate measuring devices for electronic watches.

Conventional digital rate measuring instruments that measure the time error of electronic clocks use a detection head to detect time information signals leaking from the crystal oscillator that serves as the time reference of the clock being measured or from the display device that displays the time. However, a method is used in which the time error of this detection signal is measured by a counter and then displayed on a digital display device.

However, in recent years, as a method to adjust the time accuracy of electronic watches, instead of using the conventional method of changing the crystal oscillation circuit using a trimmer capacitor, so-called digital The frequency adjustment method was adopted.

However, when measuring the rate of an electronic timepiece that employs the digital frequency adjustment described above, a leakage signal from a crystal oscillator is detected as the time information signal.

Since the measured value is different from the accuracy of the signal frequency that actually drives the time display means, detection of the time information signal requires detecting the signal leaking from the time display device. It's h.

However, when measuring the rate of an electronic watch that employs the digital frequency adjustment, the measurement period must be an integral multiple of the digital frequency adjustment period.
The disadvantages are that setting the measurement cycle becomes complicated and the measurement time becomes longer.

SUMMARY OF THE INVENTION An object of the present invention is to provide a digital rate measuring device that solves the above-mentioned drawbacks and can easily measure the rate of a watch that employs digital frequency adjustment in a short time.

In order to achieve the above object, the present invention provides a rate measuring device having a counter for measuring the time error of a time information signal generated from a clock to be measured, and a digital display device for displaying the measurement result. The present invention is characterized by the provision of rate correction means for making the displayed value different from the value displayed on the digital display device.

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is an external view of the digital rate measuring device according to the present invention, 1 is the digital rate measuring device, 2 is a digital display device, 3-digit number patterns 2at 2b, 2c, positive/negative pattern 2d, and decimal point. It has each display pattern of pattern 2e.

3 is a digital switch constituting the rate correction means;
3 corresponding to each display pattern of the digital display device 2
Digit number set switch 3a.

3b, 3c, and a positive/negative set switch 3d.

4 is a detection head that detects a time information signal leaking from a crystal oscillator of a watch to be measured.

FIG. 2 is a block diagram of the digital rate measuring instrument shown in FIG. 1, where 4 is the detection head, 5 is a signal processing circuit that amplifies the detection signal of the detection head 4 and converts it into pulses, and 6 is a pulse conversion circuit. 7 is a masking gate, 8 is a reference oscillator, which generates a reference signal of 4,320,000 Hz, and 9 is a frequency divider that divides the frequency of the signal to a frequency suitable for rate measurement. This is a counter that counts the rate of a clock, and is composed of a 7-digit up/down counter having a counting control terminal CE, a clock terminal CL, an up/down switching terminal UD, a preset terminal PR, a masking gate terminal MG, and a zero detection terminal OR1. There is.

10 is a latch circuit, 11 is a rate calculation circuit, 12 is a display drive circuit, 13 is a correction circuit, and 2 and 3 are a digital display device and a digital switch shown in FIG.

14 is a toggle type, flip-flop (hereinafter referred to as T-FF)
It is abbreviated as

)15.16 is an RS flip-flop (hereinafter referred to as R8-FF
It is abbreviated as

) 17, 18 and 19 are differentiating circuits. To explain the operation of the digital rate measuring instrument with the above configuration, first, as an initial condition, R8-FF15 is in a set state, and its output terminal Q is at a logic tt 1pp level, and R8-FF1 is in a set state.
6 is in the reset state, its output terminal Q is logic 1'0
Furthermore, the output terminal Q of T-FFi4 is at the logic "1" level.

Therefore, the counter 9 is preset to 8640000 via the preset terminal PR, and the counter 9 is preset to 8640000 via the preset terminal PR.
The up/down switching terminal UD connected to the T-FF 16 is in the down mode, and the counting control terminal CE connected to the T-FF 14 is in a non-counting state.

Furthermore, the masking gate 7 connected to R8-FF15 is open.

In this state, the timepiece to be measured is set in the detection head 4, and the digital frequency adjustment values of the timepiece to be measured are set in each switch of the digital switch 3.

Setting the rate correction amount by digital frequency adjustment of the clock to be measured is carried out by providing a plurality of frequency adjustment patterns connected to the terminals of the IC on the circuit board on which the IC of the electronic clock module is mounted, and using these patterns. A method is adopted in which the frequency is adjusted in stages by selective cutting, and the correction amount is displayed near each cutting pattern by the amount of correction obtained by cutting that pattern (e.g. 0.05 sey'day
) is printed.

Furthermore, a method has been proposed in which the correction amount obtained by the selective cutting is displayed on a digital display device in a specific mode such as rate measurement mode.

Therefore, during the manufacturing process of the watch, the setting using the digital switch is performed according to the correction amount corresponding to the cutting pattern on the board, and in the case of a completed watch, it is performed according to the correction amount displayed by calling up a specific mode. I can do it.

Then, a clock signal is detected by the RAD 4, converted into a pulse by the signal processing circuit 5, and then divided by the frequency dividing circuit 6. The first clock signal passes through the masking gate 7 as a start signal and is output to the T-FF 14. is applied to the toggle terminal T, and as a result, the T-FF14 is inverted, and the output terminal Q becomes the logic (t
, will be at jj level.

As a result, the counting control terminal CE of the counter 9 becomes ready for counting, counts the reference signal from the reference oscillator 8 applied to the clock terminal CL, and starts subtracting the preset value.

On the other hand, since the R8-FF 15 is reset by the reset pulse generated by the differentiating circuit 18 at the same time as the T-FF 14 is inverted, the masking gate 7 is closed and the subsequent clock signal cannot pass through.

Then, the counter 9 generates a signal to the masking gate terminal MG immediately before two seconds elapse from the start of the subtraction, and the counter 9 generates a signal to the masking gate terminal MG.
8-Reset FF15.

As a result, the masking gate 7 is opened again, and the next clock signal becomes a stop signal and the T-FF1
At the same time, the measurement end signal P and the measurement preparation signal P2 are generated from the output terminal via the differentiating circuits 17 and 19.

If the clock to be measured has a rate of advance, the period between the start signal and the stop signal is less than 2 seconds, so the counter 9 remains in the down mode and finishes the counting operation. If the clock to be measured has a rate of lag, the period between the start signal table and the stop signal is 2 seconds or more, so the counter 9 finishes subtracting the preset value 8640000 2 seconds after the start signal.

A zero detection signal is generated at the zero detection terminal OR, and R8-FF16
Set.

As a result, the output terminal Q of R8-FF16 becomes the logic tt
1n, and the up/down switching terminal UD of the counter 9 is switched to the up mode.

Therefore, the counter 9 is in the up mode between the zero detection signal and the stop signal, and performs addition of the reference signal.

As soon as the rate measurement by the counter 9 is completed as described above, the absolute value of the rate error in the timepiece to be measured is stored in the last three digits of the counter 9 by the measurement end signal P1.
The lead/lag information stored in R8-FF16 is latched into the latch circuit 10 as measurement information.

Then, the correction information based on the digital frequency adjustment value of the clock under test written in the correction circuit 13 by the digital switch 3 and the measurement information are processed in the rate calculation circuit 11, and the result is the true rate error. is displayed on the digital display device 2 via the display drive circuit 12.

In this example, the measurement information of the clock subjected to digital frequency adjustment of -0.05 (sec/day) is +0.07
This shows the case of (sec/aay) and is the calculation result of 1-way information: rate error +0.02 (se7day)
is displayed on the digital display.

Then, slightly later than the measurement end signal P1,
The measurement preparation signal P2 generated from the differentiating circuit 19 is applied to R8-
Preparation for measurement is completed by resetting the FF 16, switching the counter 9 to countdown mode, and presetting 8640000, and repeating the rate measurement operation using the next clock signal as a start signal.

In this embodiment, the correction information of the clock to be measured is set in units of daily difference (sec, /day), but it may also be set in units of frequency deviation (PPM). It's possible.

In addition, in the case of measurement to detect time information signals leaking from the display device of the clock under test, the digital switch 3 is set to +.
If it is set to 0.00 (5e7day), the rate will not be corrected as a result.

As described above, according to the present invention, the rate is measured by detecting the time information signal leaking from the crystal oscillator of the timepiece to be measured,
Since this method corrects the digital frequency adjustment value based on the result to find the true rate error, it is possible to quickly and easily measure the rate and adjust the time of a quartz watch that uses the digital frequency adjustment method. This not only simplifies in-store service, but also reduces costs by shortening inspection and adjustment processes on the crystal watch manufacturing line.

Furthermore, in the production line of quartz watches, the rate is generally adjusted so that the rate is slightly advanced. If the rate value to be shifted is set in the delay direction in the switch 3, one worker can adjust the rate displayed on the digital display device 2 to zero, thereby adjusting the crystal clock to the specified value. I can do it.

It is possible to improve workability.

[Brief explanation of drawings]

FIG. 1 is an external view of a rate measuring device according to the present invention, and FIG. 2 is a block diagram of the rate measuring device shown in FIG. DESCRIPTION OF SYMBOLS 1... Digital rate measuring device, 2... Digital display device, 3... Digital switch, 4... Detection head,
8... Reference oscillator, 9... Counter, 11... Rate calculation circuit, 13... Correction circuit.

Claims (1)

[Claims] 1. In a rate measuring device whose measurement target is an electronic watch that creates a time signal by digital frequency adjustment from a reference signal obtained by a crystal oscillator and displays the time, leakage from the crystal oscillator of the clock to be measured A detection head for detecting a time information signal, a counter for measuring a time error of the detected time information signal, a rate correction means for inputting digital frequency adjustment data of the clock to be measured, and a measurement value of the counter and a rate correction means. What is claimed is: 1. A digital rate measuring device comprising: a rate calculation circuit that calculates the rate of a clock to be measured from input data; and a digital display device that displays the rate calculated by the rate calculation circuit.