JPS5942341B2 - Data acquisition circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is directed to information processing apparatuses such as computers that transmit and receive data.

The prior art will be explained using FIG. 1.

Data is taken into register 1 by clock 1 and the data is transmitted to other circuits. By repeating this operation, data is sequentially transmitted to other circuits. In addition, a parity check circuit 2 is installed after register 1 to monitor data errors.
is provided. In the conventional circuit, if there is a data error in several bits of data, the parity check circuit 2 detects the parity error.

However, if clock 1, which is the clock signal for register 1, stops coming, register 1 continues to transmit the previously captured data. If there is no data error in the operation until the clock 1 stops coming, the data in the register will not have a parity error, so no abnormality detection will be performed.
An object of the present invention is to make it possible to detect an abnormality even when the clock 1 stops coming.

The feature of the present invention is that the clock signal no longer comes to the register by loading data into the register, transmitting the data to other circuits, and setting a pattern that causes a parity error before the next clock arrives. The object of the present invention is to make it possible to detect an abnormality as a parity error even in the case of a parity error. A specific example of the present invention will be explained using FIG. 2.

In the configuration of this circuit, a parity check circuit 2 is connected after a register 3 which has a clock input, a data input, and a set input whose output causes a parity error when set. Furthermore, a clock input to the clock input and set input of the register 3 is inputted in synchronization with the data and out of phase with the data. The operation of this circuit is to load data into the register 3 and transmit the data to other circuits using the clock 1. After that, register 3 is set by clock 2,
Puts the output in a parity error state. Thereafter, the next data is taken into the register 3 again by the clock 1, and the data is transmitted to other circuits. By repeating this operation, data is sequentially transmitted to other circuits. Note that the parity check circuit 2 may be operated by a timing signal generated between clock 1 and clock 2, for example. In this way, parity check circuit 2 is masked from clock 2 until clock 1 arrives, so as long as clock 1 arrives normally, the parity check circuit depends on clock 1. A parity check will be performed only on the captured data. Here, if clock 1 stops coming, register 3 is in a parity error state due to clock 2, so parity check circuit 2 detects it as a parity error.

According to the configuration of the present invention described above, when odd parity is adopted, for example, a parity error state can be realized by simply resetting register 3 (all zero data set) using clock 2, so even an extremely simple configuration can be used. Therefore, it becomes possible to detect an abnormality in which a clock does not arrive, which could not be detected by conventional circuits, as a parity error.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional data acquisition circuit, and FIG. 2 is a block diagram showing an embodiment of the present invention. 1, 3...Register, 2...Parity check circuit.

Claims (1)

[Claims] 1. In a data capture circuit that includes a register that captures data using a first clock and a parity check circuit that performs a parity check at a predetermined timing on output data from the register to other circuits, a parity check operation is performed. The data acquisition circuit is characterized in that the contents of the register are set to a parity error state by a second clock generated prior to the first clock.