JPS5943769B2 - Information transfer control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the transfer of information that changes at relatively slow time intervals via a time-division highway between a time-division channel switch network and terminal equipment connected thereto. .

In general, the data structure on the communication highway in the time division switching system is such that a group of multiple time slots is called a frame, and a group of multiple frames is called a multiframe, for example, as shown in Figure 1. There is.

In FIG. 1, a indicates a multiframe, 1 frame, c 1 time slot, and d information bit.

In this case, if we focus on one time slot, one part of the data can be configured in units of multi-frames as shown in Figure 2, and in the example of Figures 1 and 2, l6
It is possible to transfer bytes of information. As is well known, such a time-division highway is a high-speed information transfer path; for example, at a speed of 2048 kblt/sec, the time width of a time slot is approximately 3.9 μS, the period of one frame is 125 μSec, and the period of a multi-frame is is 2ms.

FIG. 3 is a general relay system diagram showing the relationship between a time division switching network and terminal devices connected thereto.

In FIG. 3, TDSW is a time division switching network, SWINFC is a switch network interface controller, DMPX is a demultiplexer,
MPX is a multiplexer, TRM is a terminal device, CPU
indicate the central control unit, respectively. In this case, the time-division highway is individually controlled by the multiplexer MPX or demultiplexer DMPX of the switching network interface controller SWINFC, which is provided outside the switching network TDSM (or the idea is the same even if it is integrated inside the switching network TDSM). The information is distributed to the information leads corresponding to the time slots. The terminal device TRM is connected to the TDSW using at least one of these time slots.

In such a case, the information receiving section and the information sending section on the terminal device side are required to operate at high speeds that can keep up with the high speed information transmission on the time division highway. In the example shown in FIG. 1, the information for one time slot is transferred by 1 byte every frame period, so the transfer period is 125 μSec. 125 μSe when using 2 or more time slots at the same time
At the end of the day, multiple bytes will be transferred.

On the other hand, in the case of an information source whose state changes at a relatively slow time interval, that is, a time interval that is sufficiently longer than the time period in the highway data structure, the information is transferred by sampling the state of the information source in the transfer cycle. The most common method is to

Therefore, when information is transferred in a multi-frame cycle as shown in Figure 2 above, and the state of the information source changes only at sufficiently long intervals compared to the multi-frame cycle, it is possible to transfer information within a certain short time. Exactly the same information is transferred in consecutive multi-frames. When the above-mentioned terminal device handles such a slowly changing information source, information should be transferred at high speed from beginning to end as described above, even though information should normally be transferred only when the state changes. action must be repeated.

The purpose of the present invention is to solve the above conventional problems,
When dealing with information sources that change slowly, the present invention provides an economical and reliable information transfer control method that focuses only on when the state changes.

According to the present invention, the above object is an information transfer control method in which a terminal device connected to a time division switch network transfers information between the time division switch network and the time division switch network using one or more time slots on a time division highway. In the terminal device, the terminal device includes a control processing circuit unit that controls all information transfer, a storage circuit unit that stores one or both of information received from the time division switch network and information sent to the network; a direct memory access control circuit section that directly controls writing and reading to and from the storage circuit section; and a counting circuit section that counts multi-frame periodic signals for controlling the time interval of the time-division highway; A counting circuit counts the multi-frame periodic signal and sends a signal to the control processing circuit to prompt the initialization process of the direct memory access control circuit, and a signal to the direct memory to permit information transfer. This is achieved by controlling the information transfer between the time division switch network and the storage circuit by configuring the information to be sent to the access control unit at different times. Explain an example.

FIG. 4 shows an embodiment of the circuit configuration diagram of the information transfer section in the terminal device for explaining the configuration of the information transfer control device in the present invention, and FIG. 5 shows a time chart showing the operation sequence of FIG. 4. show. In Figure 5, MPU is a microprocessor, RAM is random access memory, and IOC is 1
0 control circuit, DMAC is a direct memory access circuit, CNT is a counter circuit, S/P is a serial-parallel conversion circuit, P/S is a parallel-serial conversion circuit, UHW is an upper highway (TDSW direction), DHW is a down highway (terminal direction), UCH is the upper channel (TDSW
direction), DCH is down channel (terminal direction), MPX
indicates a multiplex circuit, and DMPX indicates a demultiplex circuit.

The MPU is in charge of overall transfer control and overall control of peripheral circuits connected to the data bus address bus (not shown).

Information from SWINFC is transferred to the serial/parallel conversion circuit S/P via the DCH and written to the RAM under the control of the DMkC.

Information to SWINFC is read from the RAM under the control of the DMAC, transferred to the parallel-to-serial conversion circuit P/S, and sent to SWINFC via the UCH. In this case, SWINF
Transfer operations are always performed between the SWINF and the S/P and P/S under the control of the SWINF, but true information transfer between the SWINF and the RAM is performed only when the DMAC intervenes. When the DMAC accesses the RAM, the RAM address and the number of data are set in advance to the DMAC under the control of the MPU.

The DMAC accesses the RAM area designated by the MPU for information transfer based on the time information corresponding to the channel from SWFINFC. CNT counts the multi-frame period, and M
A DMAC initialization request signal is issued to the PU.

Also, at a different time, an information transfer permission signal is issued to the DMAC. FIG. 5 shows the case in which these signals are issued alternately. Here, the data bus and address bus are MPU and D
Used by both MACs (only one at a time).
The DMAC performs direct memory access (DMA) only in the period in which a transfer permission signal is received from the CNT.

Therefore, the MPU only needs to perform the initial setting of the DMAC at another cycle, and processing can be performed with sufficient margin in terms of time intervals, and processing for transporting all terminal devices is also easy. If information were to be transferred every multiframe, the information in the time slot that the MPU would receive during DMA initial set would be transferred to RAM or R.
Cannot transfer from AM.

Even if the time is met, the time the DMAC occupies the bus will be longer, the processing time of the MPU will be reduced, and normal processing will be hindered.

Although not shown, the effect is even more significant when multiple time slots are used.

In order to prevent this from happening in another way, you can create a new UffamemO that is equal to the number of bytes in the multiframe, in addition to the RAM.
ry is installed so that the MPU can easily transfer information regardless of the multi-frame cycle, and a separate control circuit can control the Buff.
Information transfer between ermemOy and SWINFC must take place.

Therefore, it is complicated and uneconomical. Furthermore, in Figure 5,
The two signals MFCK from the CNT are designed to be output alternately, but they may also be separated by an interval.

There is no problem as long as the state of the information source changes at sufficient time intervals. As described above, according to the present invention, the microprocessor can perform processing with sufficient margin in terms of time intervals, and processing for all terminal devices can be realized economically.

[Brief explanation of drawings]

Figure 1 is a general information configuration diagram on a time division highway, Figure 2 is an information configuration diagram of one time slot in multi format,
Figure 3 is a system relay system diagram when applying the present invention;
Figure 4 is a configuration diagram of the terminal device according to the present invention, and Figure 5 is the configuration diagram of the terminal device according to the present invention.
The time charts of the control signals in the figure are shown respectively. TDSW is a time division switching network, SWINF
C is a switch network interface controller, DMPX is a demultiplexer, MPX is a multiplexer, TRM is a terminal device, CPU is a central control unit, and MPU
is a microprocessor, RAM is a random access memory, IOC is a 10 control circuit, DMAC is a direct memory access circuit, CNT is a counter circuit, and S/
P is a series-parallel exchange circuit, P/S is a parallel-serial conversion circuit, U
HW is upper highway, DHW is down highway, UCH is upper channel, DCH is down channel, MPX is multiplex circuit, and DMPX is demultiplex circuit.

Claims (1)

[Claims] 1. In an information transfer control system in which a terminal device connected to a time-division switch network transfers information to and from the time-division switch network using one or more time slots on a time-division highway, the terminal device transfers information to and from the time-division switch network. a control processing circuit unit that controls all transfers; a storage circuit unit that stores one or both of information received from the time-division switch network and information sent to the network; It has a direct memory access control circuit section that directly controls writing and reading, and a counting circuit section that counts multi-frame periodic signals for controlling the time interval of the time-division highway, and the counting circuit includes a direct memory access control circuit section that directly controls writing and reading. and transmits a signal to the control processing circuit unit to prompt the initial setting process of the direct memory access control circuit unit, and a signal to the direct memory access control unit to permit the transfer of information at different times. 1. An information transfer control method, characterized in that the information transfer control method is configured to transmit information between the time division switch network and the storage circuit section.