JPH035098B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] A frame conversion device for exchanging data between a high-speed bus and a low-speed bus, which stores a desired correspondence relationship between high-speed time slot numbers and low-speed time slot numbers in advance in a buffer control memory. Data is stored and exchanged between corresponding high-speed and low-speed time slots.

[Industrial application field]

The present invention relates to a frame conversion device, and more particularly to a frame conversion device that transfers data between a high-speed transmission path and a low-speed transmission path by converting frames.

[Conventional technology]

As a conventional frame conversion method, NTT's
MUX devices are known.

[Problems to be solved by the invention]

However, this device only has a function of regularly multiplexing low-speed frames into high-speed frames, and does not have a function of randomly arranging time slots.

[Means for solving problems]

The structure of the present invention for solving the above problems will be explained with reference to FIG. In FIG. 1, the frame conversion device according to the present invention includes a high-speed bus HSB,
Low-speed bus LSB and high-speed time slot counter
HSC, low speed time slot counter LSC,
It includes a buffer control memory BCM, a first data buffer memory DBM1, and a second data buffer memory DBM2.

The high-speed bus HSB configures each high-speed frame F _H with a predetermined number N of high-speed time slots TS _H 1 to T _{S H} N,
Transmit high-speed data.

The low-speed bus LSB consists of a predetermined number n of other low-speed time slots TS _L 1 to TS _L n, which is less than or equal to the predetermined number N described above, and configures each low-speed frame _FL having the same frame period as the high-speed frame FL _H , and transmits high-speed data. do.

The high speed time slot counter HSC calculates the time slots TS _H1 included in each high speed frame _FH .
~TS _H N for each frame.

The low-speed time slot counter LSC calculates the time slots TS _L 1 to TS L included in each of the low-speed frames F _L.
Count _TSL n every frame.

The buffer control memory BCM stores the numbers of high-speed time slots TS _H 1 to T _{S H} N and low-speed time slots.
A desired correspondence function RE with the numbers _TSL1 to _TSLn is stored in advance.

The first data buffer memory DBM1 temporarily stores data read from the high-speed bus before sending it to the low-speed bus.

The second data buffer memory DBM2 temporarily stores data read from the low-speed bus before sending it to the high-speed bus.

The count output of the high speed time slot counter HSC is used as the read address R of the buffer control memory BCM.

The low speed time slot number read from the buffer control memory BCM is set as the write address W.
The data from the high-speed bus HSB is written to the corresponding address of the first data buffer memory DBM1, and the count output of the low-speed time slot counter LSC is written to the corresponding address of the second data buffer memory DBM2 as the write address W.
Data is written from the LSB, and the count output of the low-speed time slot counter LSC is read out from the first data buffer memory DBM1 using the read address R, and the data is inserted into the corresponding time slot of the low-speed bus.
The low speed time slot number read from the second data buffer memory is set as the read address R.
Data is read from DBM2 and inserted into the corresponding time slot of high-speed bus HSB.

[Effect]

With the above configuration, between two buses with the same frame period and different transmission line speeds, it is possible to insert data extracted from one bus into the pre-corresponding time slot of the other bus. , Therefore, communication between two transmission lines with different transmission line speeds is possible.

〔Example〕

FIG. 2 shows a frame conversion device according to an embodiment of the present invention. In the figure, the high-speed bus and low-speed bus are respectively a transmission high-speed bus HSBT, a reception high-speed bus HSBR, a transmission low-speed bus LSBT, and a low-speed bus LSBT for transmission.
It is derived from LSBR. As shown in FIG. 3, one frame of both the high-speed bus and the low-speed bus is 125 μs in this embodiment. One frame of a high-speed bus is
Time slot TS0 to time slot S12
It consists of 128 time slots up to 7. One low-speed bus frame consists of channels 0 to 31.
It consists of 32 channels.

In FIG. 2, between the high-speed buses HSBT, HSBR and the low-speed buses LSBT, LSBR, there are a high-speed time slot counter HSC, a low-speed time slot counter LSC, a buffer control memory BCM, a first data buffer memory DBM1, and a first data buffer memory DBM1. In addition to the second data buffer memory DBM2, depending on the high level and low level of the clock signal CLK,
It includes a selector SEL that selects the output of the buffer control memory BCM and the output of the low-speed time slot counter LSC, determination circuits D1 to D4, and gate circuits G1 to G4.

The buffer control memory BCM has high-speed time slots TS0 to TS127 and a channel address CH0, which is a low-speed time slot, as shown in FIG.
~CH31 and communicable information indicating whether or not the corresponding time slot is in a communicable state are stored. In the illustrated example, high-speed time slot TS0 and channel address CH3 are associated, and time slot TS0
communication is possible. On the other hand, high speed time slot TS
1, TS2 is associated with an empty channel address. In other words, there is no correspondence between TS1 and TS2 and the low-speed channel addresses, so data in the high-speed time slots TS1 and TS2 cannot be transferred to the low-speed bus, and data from the low-speed bus is transferred to the high-speed time slots TS1 and TS2. It cannot be transferred to . High-speed time slot TS3 is associated with channel address CH3, but since communication is not possible with time slot TS3,
No data is exchanged between the high-speed and low-speed buses. Correspondences between other high-speed time slots and channel addresses can be similarly interpreted.

Next, the operation of the embodiment shown in FIG. 1 will be explained.

The high speed time slot counter HSC sequentially and cyclically counts the time slots of data flowing on the transmission high speed bus HSBT from 0 to 127. The output of the counter HSC becomes the read address 0-127 of the buffer control memory. Address 0~
127 corresponds to high speed time slots TS0 to TS127.

For example, when the clock signal CLK is at a high level, the selector SEL selects and outputs the read data from the buffer control memory BCM, and outputs the read data from the buffer control memory BCM.
When CLK is at low level, the output data of the low-speed time slot counter LSC is selectively output.

The determination circuit D1 determines whether the current high-speed time slot TSi (i=0, 1,
2,..., or 127)
It is determined whether CHj (j = 0, 1, 2, ..., or 31) and communication information are included, and only if both are present, gate G1 is opened and the data of that high-speed time slot TSi is transferred to the first slot. 1 data buffer memory DBM1. The write address at this time is equal to the low-speed channel number given from the selector SEL. In this way, the data of the high speed time slot TSi is stored at address j of the first data buffer memory DBM1.

When the value of the low-speed time slot counter output from the selector SEL matches the low-speed channel number corresponding to the high-speed time slot read from the buffer control memory BCM, the determination circuit D2 opens the gate circuit G2 and switches the The data read from the data buffer memory DBM1 is inserted into the low-speed transmission bus LSBT. The read address of the first data buffer memory DBM1 at this time is equal to the low speed channel number given from the selector SEL. In this way, the data in the time slot TSj of the high-speed transmission bus is inserted into the channel CHj of the low-speed transmission bus.

From high-speed bus HSBT for transmission to low-speed bus for transmission
At the same time as data is transferred to the LSBT, data is also transferred from the reception low-speed bus LSBR to the reception high-speed bus HSBR. That is, when the count output of the low-speed time slot counter LSC matches the low-speed channel number read from the buffer control memory BCM, the determination circuit D3 opens the gate G3 and converts the data from the reception low-speed bus LSBT into the second data. Store in buffer memory DBM2. The write address at this time is equal to the low-speed channel number output from the selector SEL. Further, the determination circuit D4 determines the current high-speed time slot TSi (i=
0, 1, 2, ..., or 127) and communication enable information are both included, the gate G4 is opened and the data read from the second data buffer memory DBM2 is transferred to the high-speed reception mode. Insert into bus HSBR. The read address of the second data buffer memory DBM2 at this time is equal to the low speed channel number j given from the selector SEL. In this way, the data on the channel CHj of the reception low-speed bus LSBR is transferred to the reception high-speed bus HSBR.
is inserted into the time slot TSi.

The above operations enable communication between two transmission lines with different speeds.

The present invention is not limited to the embodiments described above, and various modifications are possible. For example, when receiving data from multiple buses at the same time, as seen in time division multiplex communication, having the same number of buffer control memory and data buffer memory pairs as the number of buses can cause problems such as data dropout. It is possible to communicate with multiple buses without causing problems.

〔Effect of the invention〕

As explained above, according to the present invention, transmission lines with different transmission speeds can be used without the low-speed bus side being aware of the transmission speed of the high-speed bus, and without the high-speed bus side being aware of the transmission speed of the low-speed bus. Communication between them can be achieved relatively easily.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram showing an embodiment of the invention, Fig. 3 is a diagram showing a frame configuration in the embodiment of Fig. 2, and Fig. 4 is a diagram showing the frame structure of the embodiment of Fig. 2. FIG. 7 is a diagram showing an example of the contents of a buffer control memory in the embodiment. HSB...High speed bus, LSB...Low speed bus, HSC
...High speed time slot counter, LSC...Low speed time slot counter, BCM...Buffer control memory, DBM1...First data buffer memory, DBM2...Second data buffer memory.

Claims (1)

[Scope of Claims] 1. A high-speed bus (HSB) that configures each high-speed frame with a first predetermined number of high-speed time slots and transmits high-speed data; a second predetermined number of low-speed busses that are less than or equal to the first predetermined number; A low-speed bus (LSB) that configures each low-speed frame with the same frame period as the high-speed frame and transmits low-speed data in the time slot, and a high-speed time slot counter that counts the time slots included in each of the high-speed frames for each frame. (HSC), a low-speed time slot counter (LSC) that counts the time slots included in each of the low-speed frames frame by frame, and stores in advance a desired correspondence between the high-speed time slot number and the low-speed time slot number. a buffer control memory (BCM) for transmitting data read from the high-speed bus, a first data buffer memory (DBM1) for temporarily storing data read from the high-speed bus before sending it to the low-speed bus; It is equipped with a second data buffer memory (DBM2) for temporarily storing the data before sending out, and uses the count output of the high-speed time slot counter as a read address of the buffer control memory, and the low-speed time slot read out from the buffer control memory. The lot number is used as the write address, and the first
The data from the high-speed bus is written to the corresponding address of the second data buffer memory, and the data from the low-speed bus is written to the corresponding address of the second data buffer memory using the count output of the low-speed time slot counter as the write address. Writing, using the count output of the low-speed time slot as a read address, reads data from the first data buffer memory and inserts it into the corresponding time slot of the low-speed bus, and also uses the low-speed time slot number read from the buffer control memory. 1. A frame converting device characterized in that the data is read from the second data buffer memory and inserted into a corresponding time slot of the high-speed bus using the data as a read address.