JPS5945296B2 - Complementary MOS logic circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a complementary MO8 logic circuit which has a fast output transition time and occupies a small area.

FIG. 1 is a circuit diagram showing a conventional complementary MO8 logic circuit, and to simplify the explanation, a case of a decoder of a 6-person NAND circuit used in a 61-ary counter is shown.

In the figure, 1 to 6 are T flip-flops each having a clock terminal below, a set side output terminal Q, a reset side output terminal Q, and an IJ set end terminal metal, 7 is an inverter, and 8 to 13 are P channel MOS transistors (hereinafter referred to as 14 and 19 are N-channel MO8) transistors (hereinafter simply referred to as NMO8).
Tr).

Note that the clock shown in FIG. 2a is input to the clock terminals of the T flip-flops 1 to 6.

Further, the set side output terminals of T flip-flops 1 to 6 are each set to Qo=Q5, and this set side output terminal Qo
= The voltage waveforms of Q5 are shown in Figures 2 to 2g, respectively.

In addition, PMO8Tr 8-13 and NMO8Tr14
19 constitutes a six-man power NAND circuit, and the voltage waveform at its output terminal 20 is shown in the second diagram.

And, the 6-manpower NAND circuit has T flip-flops 1~
6 set side output terminals Qo, Q2°Qs, Q4. Since the output of Q5 and the output of the reset side output terminal are input,
When all these output voltages are 1 high" voltage, that is, when the count value is 61, the output terminal 20 of the 6-power NAND circuit becomes a "low" voltage.

Next, the operation of the complementary MO8 logic circuit having the above configuration will be explained with reference to FIGS.

First, when the clock shown in FIG. 2g is input to the clock terminal of the T flip-flop 1, the T flip-flop 1 operates and outputs the pulse shown in FIG. 2 from the set side output terminal Qo.

When this pulse is input under the clock terminal of the T flip-flop 2, the T flip-flop 2 operates and outputs the pulse shown in FIG. 2C from the set side output terminal Q1.

When this pulse is input under the clock terminal of the T flip-flop 3, the T flip-flop 3 operates and outputs the pulse shown in FIG. 2d from the set side output terminal Q2.

When this pulse is applied to the clock terminal of the T flip-flop 4, the T flip-flop 4 operates and outputs the pulse shown in FIG. 2e from the set side output terminal Q3.

When this pulse is input under the clock terminal of the T flip-flop 5, the T flip-flop 5 operates and outputs the pulse shown in FIG. 2f from the set side output terminal Q4.

When this pulse is input under the clock terminal of the T flip-flop 6, the T flip-flop 6 operates and outputs the pulse shown in FIG. 2g from the set side output terminal Q5.

And the output terminals Qo of these T flip-flops 1 to 6
, Ql, Qt, Q2, Qs, Q4
, when the values of Q5 are all “high” voltages, NM
All of the DSTRs 14 to 19 are turned on, and the output terminal 20 of the 6-man power NAND circuit becomes a peak voltage as shown in the second diagram.

Since this "low" voltage at the output terminal 20 is applied to the inverter 7, the output terminal becomes a "high" voltage.

Since this "high" voltage is input to the reset terminal R of T flip-flops 1 to 6, T flip-flop 1
~6 is reset.

The time T0 (see the second diagram) during which the output terminal 20 of the six-power NAND circuit transitions from the "high" voltage to the "low" voltage is the time T0 (see the second diagram) of the six NMOSTrs 14 to 19 connected in cascade.
is when all are ON, and for simplicity, NMO8T
If the size of r is channel width/channel length=W/L, it is proportional to 6L/W.

Therefore, within one clock time, T flip-flop 1
To reset ~6, set the time width of one clock to T.
I (see Figure 2g), then TI<TI must be true.

However, conventional complementary MO8 logic circuits, e.g.
In the decoder of a human-powered NAND circuit, the output terminal 20 is "high"
It is difficult to reduce the value of the time (T1) for transition from voltage to "low" voltage, ie, the value of 6L/W, and the counter cannot be operated with a high speed clock.

Also, six NMO8Trs are connected in cascade, but in order to convert this to the equivalent of one NMO8Tr of size W/L, the size of each NMO8Tr needs to be 6W/L, so the occupied area becomes larger.

In this way, the count number becomes large, for example 1000
The forward counter requires a 10-power NAND circuit as a decoder, and the time (T2) for its output terminal to transition from a "high" voltage to a "low" voltage is T2"10L/'W, and the above-mentioned tendency is further exacerbated. There were some noticeable drawbacks.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a complementary MO8 logic circuit which has a faster output terminal transition time, can use a high speed logic circuit, and occupies a smaller area.

In order to achieve such an object, the present invention uses one P-channel MOS transistor and n N-channel MOS transistors.
This P-channel MO
Gate electrode of S transistor and first N-channel MO
Connect the gate electrodes of the S transistors in common and connect them to the set side output terminal of the flip-flop of the N-ary counter,
The set-side output terminal or reset-side output terminal of a flip-flop of an N-ary counter is connected to the gate electrodes of the n-1 N-channel MOS transistors, and the drain electrodes of the P-channel MOS transistors and the first N-channel MOS transistors are connected to each other. A first complementary MO8 circuit and a second complementary MO8 circuit whose output terminals are commonly connected to the drain electrodes of the transistors, two P-channel MOS transistors, and one N-channel MOS transistor are connected in cascade. The gate electrode of the first P-channel MOS transistor is connected to the output terminal of the second complementary MO8 circuit, and the gate electrode of the second P-channel MOS transistor and the gate electrode of the N-channel MOS transistor are connected in common. connected to the output terminal of the first complementary MO8I-transistor and connected to the output terminal of the second P-channel MO8I-transistor.
8) A third complementary MO8 circuit in which the drain electrode of the transistor and the drain electrode of the N-channel MOS transistor are connected in common to serve as an output terminal; MO8 circuit, and third
Both ends of the complementary MO8 circuit are connected between the potential source of the first level and the potential source of the second level, and will be explained in detail below using an embodiment.

FIG. 3 is a circuit diagram showing an embodiment of a complementary MO8 logic circuit according to the present invention, and to simplify the explanation, a case of a decoder of a 6-person NAND circuit used in a 61-ary counter is shown.

In the same figure, 21 has a source electrode at the 1st level (VDI).
) The drain electrode of PMO8Tr122 connected to the potential source of PMO8Tr21 is connected to the drain electrode of PMO8Tr21, and the gate electrode of NMO8Tr122 connected to the set side output terminal Qo of T flip-flop 1 is connected to the gate electrode of PMO3Tr21. Electrode is NMO5T
NMO connected to the source electrode of r22 and whose gate electrodes are connected to the reset side output terminals of T flip-flop 2
The drain electrode of the 8Tr 24 is connected to the source electrode of the NMO8Tr 23, the gate electrode is connected to the set side output terminal Q2 of the T flip-flop 3, and the source electrode is connected to the second
NMO8Tr connected to level (ground), 25 is P whose source electrode is connected to the potential source of level (VDD)
MO8Tr.

26 is an NMO8Tr whose drain electrode is connected to the drain electrode of the PMO8Tr 25 and whose gate electrode is connected to the gate electrode of the PMO8Tr 25 and to the set side output terminal Q3 of the T flip-flop 4;

27 is an NMO8Tr whose drain electrode is connected to the source electrode of the NMO8Tr 26 and whose gate electrode is connected to the set side output terminal Q4 of the T flip-flop 5;

2B is an NMO8Tr whose drain electrode is connected to the source electrode of NMO8Tr 27, whose gate electrode is connected to the set side output terminal Q5 of the T flip-flop 6, and whose source electrode is connected to the second level (earth); The gate electrode is connected to PMO8
PMO8Tr connected to the drain electrode of Tr 25,
30 is a PMO8Tr whose source electrode is connected to the drain electrode of PMO8Tr 29 and whose gate electrode is connected to the gate electrode of PMO8Tr 21;

31 is an NMO8 whose drain electrode is connected to the drain electrode of PMO8Tr30 and to the reset terminals R of flip-flops 1 to 6, whose source electrode is connected to the second level (earth), and whose gate electrode is connected to the gate electrode of PMO8Tr30. 'rr.

Note that the PMO8Tr 21 and NMO8Tr 2
2.

23 and 24 are connected in cascade, and the first complementary MO
It consists of 8 circuits.

Also, PMO8Tr 25 . NMO8Tr 26,
27 and 28 are connected in cascade, and a second complementary MO
It consists of 8 circuits.

In addition, the drain electrode of PMO8Tr21 and the NMO8Tr
The connection point connecting the connection point with the drain electrode of No. 22 and the connection point between the gate electrode of PMO8Tr30 and the gate electrode of NMO8Tr31 is designated as 32, and the voltage waveform thereof is shown in Figure 4.

In addition, the drain electrode of PMO8Tr25 and the NMO8Tr
The connection point connecting the drain electrode of 26 and the gate electrode of PMO8Tr 29 is designated as 33, and its voltage waveform is shown in FIG. 4i.

Further, the terminal connected to the reset terminal H of the flip-flops 1 to 6 is designated as 34, and the voltage waveform applied to that terminal is shown in FIG. 4j.

Next, the operation of the complementary MO8 logic circuit having the above configuration will be explained.

First, when the set side output terminals Qs, Q4, and Q5 of the T flip-flops 1 to 6 have a high constant voltage, this "high" voltage is applied to PMO8Tr25, NMO8Tr26.
The voltage is applied to the gate electrodes 27 and 28.

Therefore, PMO8Tr25 is turned off, but NM
O8Tr 26, 27, and 28 are turned on.

Therefore, the connection point 33 is at a "low" voltage, and the PMO8
Tr 29 is also turned on.

Also, among the T-flip terminals 1 to 6, set side output terminals Qa and Q! And when Q5 is in other states, the following is true.

When the set side output terminal Q3 is “low” voltage, PMO8T
Since r25 is turned on and NMO8Tr 26 is turned off, the connection point 33 becomes 'high' voltage, and PMO8T
r29 is "off".

When the set side output terminal Q3 is at a high constant voltage and the set side output terminal Q4 or Q5 is at a low voltage, PMO8
Tr 25 and NMO8Tr 27 or 28 are in the "off" state and the connection point 33 is in a floating state, but at this time, the set side output terminal Q3 is in the state when the voltage is "low", that is, the connection point 33 is in the "0 high" state. The voltage state is maintained and the PMO
8Tr29 becomes "off-pa".

Next, when the set side output terminals Qo and Q2 and the reset side output terminal Q1 become "high" voltage, the NMO8Tr
22, 23 and 24 are all 1 on, PMO8
Since Tr 21 is "off", the connection point 32 becomes "low low voltage", PMO8Tr 30 is "on", and N
The MO8Tr31 is turned off. When the set side output terminals Qo and Q2 and the reset side output terminal Q1 are in other states, the following occurs.

When the set side output terminal Qo is “low” voltage, PMO8T
Since r 21 is turned on and NMO8Tr 22 is forced off, the connection point 32 becomes a high voltage and the PM
The O8Tr 30 is "off" and the NMO8Tr 31 is "on", so that the connection point 34 becomes a low low voltage.

Furthermore, when the set side output terminal Qo is at a "high" voltage and the reset side output terminal Q0 or the set side output terminal Q2 is at a low voltage, PMO8Tr 21 and NMO8Tr 23
Alternatively, the terminal 24 becomes "off" and the connection point 32 becomes a floating state, but at this time, the set side output terminal Q.

The state when the voltage is "low", that is, the state where the voltage at the connection point 32 is "high" is maintained, the PMO8Tr 30 is "off", the NMO8Tr 31 is "on", and the connection point 34 is kept at "low" voltage. .

As explained above, when the count content of T flip-flops 1 to 6 is 61, PMO8Tr29.

30 is "ON", NMO8Tr 31 is "OFF"
Therefore, the connection point 34 becomes a "high" voltage, all of the T flip-flops 1 to 6 are reset, and the set side output terminals Qo=Q5 all become a "low" voltage.

At this time, PMO8Tr21 and 25 are turned on, NMO8Tr 22 and 26 are turned off, connection points 32 and 33 are at high constant voltage, and PMO8Tr 22 and 26 are turned off.
8Tr 29 and 30 are “off” and NMO8T
r 31 becomes 1" and the connection point 34 again becomes a low low voltage.

The voltage waveforms at the connection points 32, 33 and 34 are shown in the fourth diagram, t and j, respectively.

In addition, the gate electrode of PMO8Tr21 and the NMOS T
When the reset side output terminal Qo is connected to the gate electrode of r22, when each T flip-flop 1 to 6 is reset, the reset side output terminal 0 is at a "high" voltage, so PMO8Tr21 is "off". '', and the set side output terminal Q2 is at 0 low'' voltage, so NM
O8Tr 24 is also "off" and node 32 is at a "low" voltage.

Therefore, node 34 holds a "high" voltage and the reset condition persists.

To avoid this, the set side output terminal of the T flip-flop is connected to the gate electrode of the PMO8Tr 21 and the gate electrode of the NMO8Tr 22.

In addition, the gate electrode of PMO8Tr 25 and the gate electrode of NMO8Tr 25
The same applies to the gate electrode of Tr 26.Next, during the time T3 when the connection point 34 transitions from the "low" voltage to the "high" voltage, NMO8Tr22, 23 and 24 are turned on, and subsequently PMO8Tr29 and 30 are turned on. This is the time to turn on PMO3Tr and N for simplicity.
If the performance of MO8Tr is considered to be equivalent and the size of each MO8Tr is W/L, it is proportional to 5L/W.

Therefore, in the 1000-decimal counter, the time for the output to reverse is proportional to 7L/W.

Therefore, when comparing the inversion time of the output of the circuit of this invention and the conventional circuit, it is found that 'r3(
=5L/W)<T□(=6L/W), in decimal counter T a (''=7 L/W) < T I
(=10L/W).

As described above, in the circuit of the present invention, the output transition time becomes faster, and an N-ary counter using a higher speed clock can be realized.
, 24.

26.27 and 2B, PMO8Tr29 and 30
are connected in cascade, so in order to convert this to the equivalent of one Tr of size W/L, NMO8Tr is size 3
The size of W/L and PMO8Tr needs to be 2W/L.

Furthermore, when comparing the occupied area between the circuit according to the embodiment of the present invention and the conventional circuit, it is found that PMO8Tr 8-13, 21
And 25, if the size of NMO8Tr31 is W/L, the former is 25W/L, the latter is 42W/L,
A circuit according to an embodiment of the present invention can be realized in an area approximately 60 times smaller than that of a conventional circuit.

As explained in detail above, the complementary form M according to the present invention
Since the O8 logic circuit can speed up the output transition time, it is possible to realize an N-ary counter using a higher speed clock.

Moreover, since the occupied area can be reduced, it is easy to integrate it into an IC.

Furthermore, since no current flows between the power supply and the ground, it has the same effect as a normal complementary MO8 circuit.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing a conventional complementary MO8 logic circuit, Figs.
The figure is a circuit diagram showing an embodiment of the complementary MO8 logic circuit according to the present invention, and FIGS. 4a to 4i are diagrams showing waveforms at various parts in FIG. 3. 1 to 6...T flip-flop, Qo=Qs・
・4 set side output terminal, Qo=Q5...Reset side output terminal, R...Reset terminal, 7...Song inverter, 8~13-PMO8Tr, i4~'is
- Song NMo5 Tr120...Output terminal, 21
・・・・・・PMO8122～24”,=・NMO8T
r125-”PMO8Tr, 26-28
"...NMO8Tr, 29-"PMO8Tr, 30~3
1...NMO8Tr, 32 and 33...curved connection point, 34...terminal. Note that the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] Eleven P-channel MOS transistors and n N-channel MOS transistors are connected in cascade, and the gate electrode of the P-channel MOS transistor and the gate electrode of the first N-channel MOS transistor are connected in common to form an N-ary counter. The set side output terminal of the flip-flop is connected to the set side output terminal of the flip-flop, the set side output terminal or the reset side output terminal of the flip-flop of the N-ary counter is connected to the gate electrodes of n1 N-channel MOS transistors, and the A first complementary MO8 circuit and a second complementary MO8 circuit whose drain electrode and the drain electrode of the first N-channel MOS transistor are commonly connected to serve as an output terminal, two P-channel MOS transistors, and one N-channel MOS transistors are cascade-connected, and the gate electrode of the first P-channel MOS transistor is connected to the second complementary MOS transistor.
Connected to the output terminal of 8 circuits and connected to the second P-channel MO
8) - Connect the gate electrode of the transistor in common and the gate electrode of the N-channel MOS transistor to the output terminal of the first complementary MO8t transistor, and
A third complementary MO8 circuit is provided, which connects the drain electrode of the channel MOS transistor and the drain electrode of the N-channel MOS transistor in common, and uses the output of the output terminal as a reset power source for the N-ary counter. and a second level potential source.
8 circuit, a second complementary MO8 circuit and a third complementary M
A complementary MO8 logic circuit characterized by connecting an O8 circuit.