JPS5946074B2 - Address translation buffer control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an address translation buffer control method, and particularly to a data processing device having an address translation buffer that stores copy information of a main memory protection key along with a pair of logical addresses and real addresses. In the case of operations that do not require referencing or address translation, the operation is executed without using the data read from the address translation buffer, thereby increasing the efficiency of using the address translation buffer and speeding up the operation. Regarding the control method.

In order to reference the main memory protection key (hereinafter abbreviated as MSKEY) at high speed, there is a method of creating a copy of MSKEY in an address translation buffer (hereinafter abbreviated as TLB).

According to this method, access to the TLB is required not only when the system is operating in virtual mode but also when the system is operating in real mode. because,
This is because it is necessary to refer to MSKEY even in the real mode. In this case, the real address is placed in the virtual address section of the TLB to perform an apparent address conversion operation. Furthermore, some operations are accessed with a real address and do not perform a proactive check (by MSKEY). Conventionally, even in the case of such special operations, the TLB has been accessed in order to unify the operations and make the circuit format common. However, according to this method, the following drawbacks arise when the above-mentioned special operations are executed. (1)T
Information that is originally unnecessary is registered in the LB, and the efficiency of using the TLB decreases.

(2) Action 5 for registering the above unnecessary information in TLB
processing flow is required, which reduces the performance of the processing device.

The present invention increases the efficiency of TLB usage by making it appear as if the address translation and flow section check by the TLB were performed normally when the above-mentioned special operation is recognized, without registering unnecessary information in the TLB. , an object of the present invention is to improve the performance of a processing device, and for this purpose, the present invention has an address translation buffer that stores copy information of a main memory protection key along with a pair of logical addresses and real addresses that correspond to each other. In a data processing device that can obtain a real address by accessing a main memory protection key and refer to a main memory protection key, a flag is set when neither address translation nor reference to the main memory protection key is required. The present invention is characterized in that when the flag is on, an address translation success signal and a flow section check normal signal are generated regardless of the contents of the address translation buffer.

Hereinafter, the present invention will be explained with reference to the drawings.

The figure shows an address translation buffer control circuit according to an embodiment of the present invention. In the figure, 1 is a valid address register, 2 is a flag that is set when neither address translation nor MSKEY reference is required, and 3 is a TLB. 3-1 is a logical address section, 3-2 is a STO-1D section, 33 is a valid bit section, 3-4 is a real address section, 3-5 is an MSKEY section, and 4 is a write to TLB. register, 5 is a read register from TLB, 6 is a comparison circuit for detecting successful address conversion (TLBMATCH), 7 is MSKEY and PS read from TLB
A comparison circuit that compares WKEY, 8 is a register in which STO-D from the STO stack is set, and indicates the space currently being worked on, and 9 is a register that indicates the address of effective address register 1 when flag 2 is on. Low level COll
), 10 is S when flag 2 is on.
The address of TO-1D register 8 is set to low level (1W
011), 11 is a prefix conversion circuit, 12 is a gate that selects the address from the prefix conversion circuit 11 when flag 2 is on, and T when flag 2 is off.
A selection circuit 13 selects read data from the real address section 3-4 of LB3, when flag 2 is on or P
SWKEY is all 1W0! ? This is a gate that forcibly outputs a flow section check normal signal when . Note that the output of flag 2 is the logical address section 3-1 of TLB3.
, the STO-1D section 3-2, and the valid bit section 3-3 are input to the chip select terminals of each memory so as to force the outputs of the memories to ``0'' (the valid bit is at a low level and valid). Examples of the types of operations in which flag 2 is set include the following operations.

1 Access to the address translation table When the TLB is accessed and no address match is detected, the hardware performs segment table access and page table access to obtain the real address, but the access at that time is MSKEY. It is not necessary to refer to .

52--Access to the to-ware fixed area that occurs from the to-ware itself.

There is a storage area, also called a prefix area, for saving and restoring PSW at the time of an interrupt, and one-to-ware information at the time of machine check, and access to these areas is automatically performed by the hardware. 3 Buffer invalidation When a store is executed from the other side's CPU in a multiprocessor system or from a channel in a single processor system to the main memory, it is necessary to ensure that the buffer of the own CPU and the main memory are duplicated. Yes, but there is access for that purpose.

4 Purge TLB An operation that invalidates all the contents of TLB ~ 5 Partial package TLB MS by SSK (SetstOragekey) command
When KEY is rewritten and IPTE (Inval
When a page is invalidated by the ldatePageTableEntly) instruction, the hardware
It is necessary to check the LB and, if the corresponding page is in the TLB, invalidate it.

Flag 2 is set when a control unit (not shown) detects a condition that does not require both address translation and main memory protection key reference. When flag 2 turns on, the logical address section 3-1 and STO-1D section 3 of TLB3
-2, the output of the valid bit section 3-3 is forced to a low level. Furthermore, since the address of the effective address register 1 and the output of the STO-1D register 8 are also forced to the low level by gates 9 and 10, respectively, the inputs of the comparison circuit 6 are all 1011, and the TLBMA
The TCH conditions are obtained, and the comparison circuit 6 outputs an address conversion success signal. Further, since flag 2 is turned on, the output of gate 13 becomes low level regardless of the output of comparator circuit 7, and a flow section check normal signal is obtained. Further, when flag 2 is on, the value of effective address register 1 is converted into a real address by prefix conversion circuit 11, and then sent to an arithmetic unit (not shown) through selection circuit 12.

In the above embodiment, a method is used in which all the inputs of the comparator circuit 6 are set to low level by controlling the chip select signal of the TLB 3 and controlling the gates 9 and 10. However, if time constraints are not severe, the gate 9 , 10, etc., it is also possible to obtain the TLBMATCH signal by ORing the output of the comparator circuit 6 and the output of the flag 2.

As described above, according to the present invention, the address conversion success signal and the flow section check normal signal can be generated without using the read data from the TLB.
When executing special operations that do not require address translation or flow section checking, control formats can be unified without registering essentially unnecessary information in the TLB.

[Brief explanation of the drawing]

The figure shows an address translation buffer control circuit according to an embodiment of the present invention. In the figure, 1 is an effective address register, 2 is a flag, 3 is TLB14 is a write register to TLB, 5 is a read register from TLB, 6 and 7 is a comparison circuit, 8 is a STO-1D register, 11 is a prefix conversion circuit,
12 is a selection circuit.

Claims (1)

[Claims] 1. It has an address translation buffer that stores copy information of the main memory protection key along with pairs of logical addresses and real addresses that correspond to each other, and can access the address translation buffer to obtain the real address and refer to the main memory protection key. A data processing device configured to have a flag that is set when an operation that does not require both address translation and main memory protection key reference is provided, and when the flag is on, regardless of the contents of the address translation buffer. An address translation buffer control method characterized in that an address translation success signal and a protection check normal signal are generated.