JPH0234059B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device, particularly a data processing system in which a TLB is provided within a storage device or is comprised of elements that operate at substantially the same speed as the storage device itself and is provided separately from the storage device. , only if a page cross actually occurs during address update processing for a given logical address.
The present invention relates to a data processing device that performs TLB index processing and also allows address update processing to be performed correctly even when the system is operating in real mode.

In a data processing system that uses a virtual memory method, TLB (Translation Lookahead
For example, when a conditional branch is established and a new logical address is given, or when a page cross occurs while updating an address in a page in a logical address, etc. Index processing is performed on the TLB to convert logical page addresses to real page addresses.

Conventionally, in this type of data processing system, when determining the occurrence of the above-mentioned page cross, the determination is made based on the operand in address update processing, that is, the address within the page and the number to be added to or subtracted from it. I was trying to do that. For example, if the above operand is a relatively small number such as +1 or +2, the occurrence of page crosses is constantly checked and based on the check results,
Decide whether or not to index the TLB, and on the other hand, if the operand above is a relatively large number such as +8, assume in advance that a page cross will occur and be sure to perform TLB index processing. was.

However, if the above method is adopted when the operating speed of the TLB is approximately the same as that of the storage device, if the operand is relatively large, the
As a result of having to perform TLB index processing, undesired TLB index processing must be performed even if a page cross does not actually occur, which increases the overall time required for memory access. I didn't get it. This thing is
The same applies when the TLB is provided as part of the storage device.

The present invention is not limited to systems that use only virtual storage, but can also be applied to systems that also use real storage.
The purpose is to perform index processing for the TLB only when a page cross actually occurs, and to perform address translation processing efficiently. Furthermore, the present invention allows the system to be
mode, it detects that an incorrect access address has been generated, and if this detection is made, the generated access address is corrected to obtain the correct access address. The purpose is to reduce the address update calculation time. Therefore, the data processing device of the present invention indexes the TLB when a page cross occurs during address update processing for a given logical address. It is divided in advance into a first address part consisting of bits and constituent bits of the address within the page, and a second address part consisting of other constituent bits, and when performing consecutive accesses, the first address part is updates the address using an arithmetic unit having the same arithmetic bit width as the constituent bits of the first address part, and makes only the in-page address part a memory access address,
For other page address parts, the values that have already been set are used, and at the same time, a page cross check is performed based on the calculation result of the above-mentioned arithmetic unit, and when a page cross occurs, a carry or In order to use the logical address obtained by propagating the borrow as the memory access address, at least a carry to the page address is used as a check signal as a check condition for a page cross, and the system operation mode is set to either virtual address or real address mode. Even if the same page/
It is characterized by the ability to perform cross checks. The present invention will be described below with reference to the drawings.

The figure shows the configuration of an embodiment of a data processing device according to the present invention.

In the figure, 1 is a central processing unit, 2 is a storage device, 3 is a logical address register to which a given logical address is set, and 3-1 is the first address part according to the present invention, which is a part of the logical address. Some constituent bits of the page address (in the figure, the bits from the 8th bit position to the 14th bit position) and constituent bits of the internal page address of the logical address (in the figure, the bits from the 15th bit position to the 23rd bit position) 3-2 is the second address part according to the present invention, and the other constituent bits of the logical address (in the case of the figure, the bits from the 0th bit position to the 7th bit position) 4 is an operand register in which the operand to be added or subtracted from the first address part 3-1 in the above logical address is set; 5 is an arithmetic unit which registers the above logical address. First address part 3 inside
-1 and the operand in the operand register 4 are added or subtracted, 6 is TLB
(Translation Lookahead Buffer), which is composed of components whose operating speed is the same as or close to that of the storage device 2 (it may be disposed within the storage device 2); 7 is a check circuit; 8 is an access address register for detecting the occurrence of a page cross; 8 is an access address register in which a logical address or address translation processing result, that is, a memory access address, is set; 9 to 10 are respective access address registers; Not Gate, 11 and 12 are respectively and.
13 is an OR gate, 14 is a bit signal at the 15th bit position in the logical address, 15 is a carry or borrow signal from the 8th bit position in the calculation result by the arithmetic unit 5, and 16 is a signal from the arithmetic unit 5. They respectively represent a carry or borrow signal from the 0th bit position in the calculation result. The processing operations in each case will be explained below by classifying the system into cases in which it operates in virtual address mode and cases in which it operates in real address mode. In this case, it is assumed that the arithmetic unit 5 performs addition processing and accesses are performed continuously.

[] When the system is in virtual address mode.

(1) When a page cross does not occur during address update processing during continuous access, that is, (a) When signal 14 is logic "0" and signal 15 is logic "0" or logic "1". Or (b) When the signal 14 is a logic "1" and the signal 15 is a logic "0", the output of the check circuit 7 becomes a logic "0" and no index processing is performed on the TLB 6. The addition result of arithmetic unit 5 is the 15th address register of access address register 8.
It is set in the bit area from the bit position to the 23rd bit position. In this case, it is assumed that the logical address has already been converted and the real page portion of the desired access address has been set in the 0th bit position to the 14th bit position of register 8.

(2) On the other hand, if a page cross occurs during address update processing, that is, signals 14 and 15
When both are logic "1", the output of the check circuit 7 becomes logic "1", and index processing for TLB 6 is performed. First, the addition result of the arithmetic unit 5 is set in the area from the 8th bit position to the 23rd bit position of the register 8, and the second address part 3-2 is set to the area from the 0th bit position to the 7th bit position of the register 8. Set in bit area. At this time, if the signal 16 is logic "1", the information in the area of the second address section 3-2 is subjected to +1 processing and then set in the register 8. An updated logical address is therefore obtained in register 8.

Next, from the 0th bit position of register 8 to the 14th bit position
TLB by page address at bit position
6 is indexed, and the index result, ie, the page address, is set in the bit area from the 0th bit position to the 14th bit position of register 8. That is, the desired access address consisting of the real page address and the in-page address after address update processing is stored in register 8 according to the TLB index.
An address will be obtained.

[] When the system system is in real address mode.

(1) When the output of the page cross check circuit 7 becomes logic "0", the second address part 3-2 in the logical address at the beginning of continuous access is from the 0th bit position to the 7th bit position of the register 8. The 8th bit position to the 14th bit position of the first address section 3-1 is set to the 8th bit position to the 14th bit position of the register 8. The result of addition by the arithmetic unit 5 is set in the bit area from the 15th bit position to the 23rd bit position of the register 8. That is, an access address is generated as desired, consisting of a real page address that is the same as the page address in the logical address, and an in-page address that is the result of updating the in-page address in the logical address.

(2) On the other hand, when the output of the page cross check circuit 7 becomes logic "1", the page address section of the access address register 8 is also updated.

The addition result of the arithmetic unit 5 is set in the bit area from the 8th bit position to the 23rd bit position of the register 8, and is further stored in the second address section 3-2.
2 is set in the bit area from the 0th bit position to the 7th bit position of the register 8.
At this time, if the signal 16 is logic "1", the information in the area of the second address section 3-2 is +1.
It is set in register 8 after processing. An updated logical address, ie the desired access address, is thus obtained in register 8.

The above description of the processing operation is for the case where the arithmetic unit 5 performs the addition process, but the same process is performed when the arithmetic unit 5 performs the subtraction process.
Therefore, the page crossing detection signal, OR
When the output of the gate 13 is off, only the calculation for the first address part is required during continuous access.

As is clear from the above description, according to the present invention, even when the operand is relatively large, it is determined whether or not a page cross actually occurs, and only when a page cross occurs, the second address is Since calculations for the second address part and index processing for the TLB are performed, unnecessary calculations and index processing for the second address part, which were conventionally performed for the TLB, can be omitted, reducing the overall time required for memory access. Furthermore, common control is possible in both virtual address and real address modes.

[Brief explanation of drawings]

The figure shows the configuration of an embodiment of a data processing device according to the present invention, in which 2 is a storage device, 3 is a logical address register, 3-1 is a first address section, and 3-2
4 represents the second address part, 4 represents the operand register, 5 represents the arithmetic unit, 6 represents the TLB, 7 represents the check circuit, and 8 represents the access address register.

Claims (1)

[Claims] 1 If a page cross occurs during address update processing for a given logical address,
In a data processing device that indexes a TLB, the logical address is divided into a first address part consisting of some constituent bits of a page address and constituent bits of an intra-page address, and a second address part consisting of other constituent bits. When performing consecutive accesses, the address of the first address part is updated by an arithmetic unit having the same operation bit width as the constituent bits of the first address part, and the addresses within the page are updated. only part is the memory access address, and the other page/
The address part uses the value that has already been set, and at the same time checks for page crosses based on the calculation results of the above arithmetic unit. When a page cross occurs, a carry or borrow is propagated to the second address part. The logical address obtained by
As a check condition for page crosses to be used as access addresses, at least a carry to a page address is used as a check signal, and the same page cross check is performed regardless of whether the system operation mode is virtual address or real address mode. A data processing device characterized by being able to perform the following operations.