JPS5946396B2 - Display control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a display leg scheme, and more particularly to a display leg scheme in a direct memory access (DMA) transfer scheme.

Currently, most display devices, including cathode ray tubes, are controlled by microprocessors, and therefore it is necessary to access memory areas in order to display the desired display.

Therefore, for example, in the conventional display side leg system in a cathode ray tube display device, one byte of the contents of a predetermined address in the memory is extracted and transferred to the display device in the first half of the ICPU cycle time, and the content is transferred to the display device in the second half. The data input to the control unit is written into memory by a microprocessor. Therefore, in this conventional method, the control section of the display device is in a standby state during the latter half of each cycle time, which has the disadvantage that the efficiency of data transfer to the display device is low. Therefore, in order to apparently shorten the time in the second half of each cycle time, which is the waiting time, 2 bytes of data are retrieved from the memory in the first half, and these 2 bytes of data are made into tandem, and one cycle A method is used in which 2 bytes of data cannot be displayed in time, but
Although this method improves the transfer efficiency, it has the disadvantages that the device configuration is complicated and the price is high. Therefore, an object of the present invention is to provide a display side leg system that has a simple device configuration and has good transfer efficiency.

In order to achieve the above object, the present invention provides an ICPU of a display system using a direct memory access transfer method.
The cycle time is made up of a plurality of display data transfer timings and processor access timings. Hereinafter, the system of the present invention will be explained in detail with reference to illustrated embodiments. FIG. 1 shows a block diagram of a display restraint device for performing display restraint according to the method of the present invention.

The display control device 1 includes a display device 2 including a cathode ray tube.
This is a device for controlling display using the direct memory access transfer method, and includes a processor (CPU) 3 for processing display data, a memory 4, and a timing pulse generator 5. The timing pulse generator 5 divides one CPU cycle time T of the display control device 2 into three equal parts, and uses two of them as display timing and the remaining one as CPU access timing, as shown in FIG. Timing pulse φ1 shown in a-c
, φ2, φ3 are output. Timing pulse φ1,
φ2 is input to two inputs of the OR circuit 6, and the synthesized display timing pulse S1 as shown in FIG. The address signal S2 from the display address generator 7 is applied to the other input of the AND circuit 8. The display address generator 7 is for generating an address signal for retrieving desired display data stored in the memory 4, and is used when the composite display timing pulse S1 becomes "1". In this case, when the timing pulse φ1 is "1", the display address generator 7 outputs the address signal S2 specifying the address at address n, and then the timing pulse φ2 " 1] is output.In other words, in one CPU access time, two addresses are designated and two bytes of data are retrieved from the memory 4.Timing '2 bytes of data D taken out from the memory 4 by the lenses φ1 and φ2.
Dn+, is simultaneously input to one input of each of AND circuits 9 and 10, but timing pulses φ1 and φ2 are input to the other inputs of these AND circuits 9 and 10, respectively. Data D is output from the circuit 9. is taken out, and data D is output from the AND circuit 10. +1 is retrieved and these data D. , DO+1 are stored in 1-byte buffer memories 11 and 12, respectively. These stored contents are first stored as data D by the control signal S3 from the control circuit 13. is read out and input to the character generator 15 via the OR circuit 14, resulting in data D. The character pattern data PDn determined by is outputted below the control cape of the control signal S3, and then the data D. +1 is read out, and data D is similarly read out from the character generator 15. Character pattern data PDO+1 determined by +1 is output. Character pattern data from the character generator 15 is sent to the parallel/serial conversion circuit 1
6 into a bit serial signal, and this converted output S4 is supplied to the display device 2. On the other hand, when the timing pulse φ3 becomes "1-1", it becomes the processor access timing, and the composite display timing pulse S1 becomes "0".
” and the address signal S is output from the display address generator 7.
2 is prohibited from being output, the AND circuit 17 is opened, and the CPU address signal S5 from the processor 3 is supplied to the memory 4 via the OR circuit 18. During this processor access timing period, this CPU address signal S5 and the access signal S6 from the processor 3
The contents of the memory 4 are changed, added, deleted, etc., depending on the contents. When one CPU access time ends in this way, when the next one CPU access time begins, the same operation is performed again, addresses n+2 and n+3 of memory 4 are specified, and data Dn+2 and D0+3 are output. , and further these data are sent to the character generator 15 as described above.
character pattern data PDO+1, PD0+
3 is obtained.

When the timing pulse φ3 becomes "1", the display operation is temporarily stopped, and the processor 36 executes the required data processing operation. In the display control device shown in Fig. 1,
Divide 1 CPU access time T into three equal parts and divide 2 of them into three equal parts.
The present invention is limited to two display data transfer timings (timings determined by φ1 and φ2) and one processor access timing (timing determined by φ3). However, the method of the present invention is limited to such timings. However, in general, the time T may be divided into N equal parts (N>2), one of the periods may be used as the processor access timing, and the remaining period (N-1) may be used as the display data transfer timing.

Therefore, conventionally, when there is a conflict between a processing request in a processor and a display processing request, it is necessary to choose between temporarily erasing the screen or temporarily stopping processing by the processor. However, according to this method, since a processor access time is always provided for each CPU access time, the above-mentioned disadvantages are not only completely eliminated, but also it is possible to display multiple data during one CPU access time. Since display data is transferred, the transfer efficiency can be extremely high, and the circuit can be extremely simple. According to the present invention, as described above, it is possible to provide an excellent display control method that can quickly respond to processing requests from a processor and has extremely high transfer efficiency without complicating the configuration of the device.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIGS. 2a to 2d are time charts for explaining the operation of the embodiment of FIG. 1.

Claims (1)

[Claims] 1 a processor having a predetermined operating cycle time;
The display device includes a display device that displays a plurality of display data during the operation cycle, and a memory having a storage area used by the processor and an area where the display data is stored. In a display control method in which the memory is accessed to capture and display the display data during a period other than the period in which the processor is accessed, a plurality of clocks each having a different phase are generated within the predetermined operation cycle time. means for synchronizing with the clock and dividing the predetermined operation cycle time into a plurality of transfer timings for transferring addresses corresponding to the plurality of display data to memory and an access timing of the processor; an address counter that is counted up according to the transfer timing and indicates a storage address of the display data to be transferred; a plurality of buffer memories each storing a plurality of display data read from the memory; a gate for writing display data during a period in which corresponding clocks of different phases are inputted to each buffer memory;
A display control method characterized in that the plurality of pieces of display data are sequentially loaded into different buffer memories within the predetermined operation cycle time, and the display data in the buffer memories are displayed in the order in which they were loaded.