JPS5946421B2 - Lead frame for semiconductor devices - Google Patents
Lead frame for semiconductor devicesInfo
- Publication number
- JPS5946421B2 JPS5946421B2 JP52079355A JP7935577A JPS5946421B2 JP S5946421 B2 JPS5946421 B2 JP S5946421B2 JP 52079355 A JP52079355 A JP 52079355A JP 7935577 A JP7935577 A JP 7935577A JP S5946421 B2 JPS5946421 B2 JP S5946421B2
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- lead
- element mounting
- semiconductor devices
- mounting part
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は改良された半導体装置用リードフレームに関す
るものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improved lead frame for a semiconductor device.
大出力用半導体装置は、従来セラミックケース或いは金
属ケース等を使用していたが、コストダウンを計るべく
量産性の良い樹脂封止型が採用されるようになつてきた
。High-output semiconductor devices have conventionally used ceramic cases or metal cases, but in order to reduce costs, resin-sealed devices that can be easily mass-produced have come to be used.
この樹脂封止型半導体装置はリードフレームを用いて製
造するのが一般的である。このリードフレームの一般的
な形状は第１図の平面図に示すように、コバール等の金
属薄板を写真蝕刻法或いはプレス加工により、外枠１ａ
−Ｉｂ間に半導体素子２を固着するための素子載置部３
、リード４、リード４を固定している内枠５がそれぞれ
一体的に形成されている。このリードフレームの表面は
、部分的に或いは全面に金属層がメッキにより設けられ
ている。特に大出力用装置に用いられる従来のリードフ
レームの場合は、例えば第２図（第１図のＡ−Ａ’断面
図）に示すように、全面に熱伝導性の良い銀メッキが１
０〜１５ミクロンの厚さで一様に設けられている。この
ようなリードフレームを用いた樹脂封止型半導体装置は
、先ず素子載置部３に金−シリコン合金片あるいは金片
Ｔを介して半導体素子２を置き、約４００℃に加熱する
と半導体素子２は金ーシリコン合金片或いは金片Ｔと金
一シリコン共晶合金を形成して素子載置部３に固着され
る。This resin-sealed semiconductor device is generally manufactured using a lead frame. The general shape of this lead frame is as shown in the plan view of FIG.
- Element mounting part 3 for fixing the semiconductor element 2 between Ib
, the lead 4, and the inner frame 5 to which the lead 4 is fixed are each integrally formed. The surface of this lead frame is partially or entirely provided with a metal layer by plating. In particular, in the case of conventional lead frames used in high-output devices, as shown in Figure 2 (A-A' cross-section in Figure 1), one layer of silver plating with good thermal conductivity is applied to the entire surface.
The thickness is uniformly 0 to 15 microns. In a resin-sealed semiconductor device using such a lead frame, the semiconductor element 2 is first placed on the element mounting portion 3 via a gold-silicon alloy piece or a gold piece T, and heated to about 400°C. is fixed to the element mounting portion 3 by forming a gold-silicon alloy piece or a gold-silicon eutectic alloy with the gold piece T.
次に素子２とリード４とを金属細線８を用いて接続する
わけであるが、リード４の表面の銀層９は、前工程での
加熱により硬度が低くかつ厚さが１０ミクロン以上ある
ため、金属細線８は接着部がこの銀層９に沈み、接着面
において金属細線８は十分な接着面積を得られない。従
つて金属細線８とリード４との強固な接着を得ることが
できないので、高信頼性を有する大出力用半導体装置を
得ることは困難である。Next, the element 2 and the lead 4 are connected using the thin metal wire 8, but since the silver layer 9 on the surface of the lead 4 has low hardness due to heating in the previous process and has a thickness of 10 microns or more. The bonded portion of the thin metal wire 8 sinks into the silver layer 9, and the thin metal wire 8 does not have a sufficient bonding area on the bonding surface. Therefore, it is impossible to obtain strong adhesion between the thin metal wires 8 and the leads 4, making it difficult to obtain a high-output semiconductor device with high reliability.
本発明は上述した点に鑑み、信頼性の高い大出力用樹脂
封止型半導体装置を得るために適用可能なリードフレー
ムを提供するものである。In view of the above-mentioned points, the present invention provides a lead frame that can be applied to obtain a highly reliable high-output resin-sealed semiconductor device.
即ち、本発明は金属薄板を写真蝕刻法あるいはプレス加
工してリード線の集合体及び素子載置部を少なくとも含
むリードフレームを形成し、素子載置部には高熱伝導性
を有する金属層が厚く、リードにはそれよりも薄い金属
層が設けられたものである。That is, in the present invention, a lead frame including at least an assembly of lead wires and an element mounting part is formed by photolithography or press processing of a metal thin plate, and the element mounting part is coated with a thick metal layer having high thermal conductivity. , the leads are provided with a thinner metal layer.
以下本発明を実施例について説明する。第３図は本発明
によるリードフレームの断面図で第１図のＡ−Ａ’に相
当する部分を示す。第１図を参照して説明すると、２５
０ミクロン厚のコバール薄板を写真蝕刻法またはプレス
加工して外枠１ａ−Ｉｂ間に半導体素子２を固着するた
めの素子載置部３、リード４、リード４を固定するため
の内枠５を一体的に形成する。The present invention will be described below with reference to Examples. FIG. 3 is a sectional view of a lead frame according to the present invention, showing a portion corresponding to AA' in FIG. To explain with reference to Figure 1, 25
An element mounting part 3 for fixing the semiconductor element 2 between the outer frame 1a and Ib, leads 4, and an inner frame 5 for fixing the leads 4 are made by photolithography or press processing of a Kovar thin plate having a thickness of 0 microns. Form integrally.
次にリードフレームの表面処理を行うわけであるが、先
ず部分メツキ法にて素子載置部３の素子載置面及び素子
載置部３を支える支持枠６の一面のみに第３図に示す如
く１０〜１５ミクロン厚の銀層９を設ける。次に全面に
２〜４ミクロン厚の銀層ｑを施こす。このようにして製
作されたリードフレームを使用すれば、半導体素子とリ
ードを金属細線を介して接続する場合、リードの表面金
属層は２〜４ミクロンと薄く、金属細線の沈む量は小さ
いので所望の接着面積を持つた強固な接続を得ることが
できる。又半導体素子で発生した熱は、素子載置部及び
支持枠上に設けられた厚い銀層等の高熱伝導性の金属層
により放散されるので、高信頼性を有する大出力用樹脂
封止型半導体装置を得ることができる。なお、本実施例
では、部分メツキと全面メツキの組合せについて述べた
が、部分メツキと部分メツキとの組合せでも同様な効果
が得られることは当然である。Next, the surface treatment of the lead frame is performed. First, a partial plating method is used to coat only the element mounting surface of the element mounting section 3 and one surface of the support frame 6 that supports the element mounting section 3 as shown in FIG. A silver layer 9 having a thickness of 10 to 15 microns is provided. Next, a 2-4 micron thick silver layer q is applied over the entire surface. If a lead frame manufactured in this way is used, when connecting a semiconductor element and a lead via a thin metal wire, the surface metal layer of the lead will be as thin as 2 to 4 microns, and the amount of sinking of the thin metal wire will be small, making it possible to achieve desired results. A strong connection can be obtained with a bonding area of . In addition, the heat generated by the semiconductor element is dissipated by a highly thermally conductive metal layer such as a thick silver layer provided on the element mounting part and support frame, making it possible to use a high-output resin-sealed type with high reliability. A semiconductor device can be obtained. In this embodiment, a combination of partial plating and full plating has been described, but it goes without saying that a similar effect can be obtained by a combination of partial plating and partial plating.
第１図は一般的なリードフレームｉ図、第２図は第１図
Ａ−Ｎに於ける従来のリードフレームの断面図を、第３
図は第１図Ａ−Ｎに於ける本発明によるリードフレーム
の断面図をそれぞれ示す。
１ａ，１ｂ・・・・・・外枠、２・・・・・・半導体素
子、３・・・・・・素子載置部、４・・・・・・リード
、５・・・・・・内枠、６・・・・・・支持枠、７・・
・・・・金−シリコン片あるいは金片、８・・・・・・
金属細線、９，９／・・・・・・銀層。Fig. 1 is a diagram of a typical lead frame, Fig. 2 is a sectional view of a conventional lead frame in Fig. 1 A-N, and Fig.
The figures show cross-sectional views of a lead frame according to the invention in FIGS. 1A-N, respectively. 1a, 1b...Outer frame, 2...Semiconductor element, 3...Element mounting portion, 4...Lead, 5... Inner frame, 6...Support frame, 7...
...Gold - silicon piece or gold piece, 8...
Fine metal wire, 9,9/...silver layer.
Claims (1)
導体素子を固着するための素子載置部を一体的に形成し
たリードフレームに於いて、素子載置部の表面に熱伝導
性の良好な金属層がリード線の表面に設けられた金属層
よりも厚く設けられていることを特徴とする半導体装置
用リードフレーム。1. In a lead frame in which a metal thin plate is processed to integrally form an assembly of a large number of lead wires and an element mounting part for fixing a semiconductor element, the surface of the element mounting part has good thermal conductivity. A lead frame for a semiconductor device, characterized in that the metal layer is thicker than the metal layer provided on the surface of the lead wire.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP52079355A JPS5946421B2 (en) | 1977-07-01 | 1977-07-01 | Lead frame for semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP52079355A JPS5946421B2 (en) | 1977-07-01 | 1977-07-01 | Lead frame for semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5413775A JPS5413775A (en) | 1979-02-01 |
| JPS5946421B2 true JPS5946421B2 (en) | 1984-11-12 |
Family
ID=13687583
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP52079355A Expired JPS5946421B2 (en) | 1977-07-01 | 1977-07-01 | Lead frame for semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5946421B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5866641U (en) * | 1981-10-28 | 1983-05-06 | 九州日本電気株式会社 | semiconductor equipment |
| JPS59145550A (en) * | 1983-02-09 | 1984-08-21 | Matsushita Electronics Corp | Lead frame |
| JPS62114254A (en) * | 1985-11-13 | 1987-05-26 | Mitsui Haitetsuku:Kk | Manufacture of lead frame |
-
1977
- 1977-07-01 JP JP52079355A patent/JPS5946421B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5413775A (en) | 1979-02-01 |
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