JPS5947381B2 - magnetic bubble storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a magnetic bubble storage device that is being put into practical use as a file storage device.

Magnetic bubble storage devices are desired to have larger capacity, smaller size, lower cost, and lower power consumption.

One way to meet these demands is to divide a large number of bubble memory chips into multiple memory planes and implement the in-plane magnetic field (a large power consumption source) required to drive the chips. A method is used to selectively supply units. In such a magnetic bubble storage device, the driving timing for the memory plane selected according to the plane selection address is determined by the internal address of the memory loop of the bubble memory chip in that plane and the external address according to the access request. must be determined for each access request.

This requires a means for managing the internal addresses of the memory loops of the bubble memory chips within each memory plane, corresponding to each memory plane. Conventionally, since it is necessary to update the internal address according to the number of driving steps of the in-plane magnetic field, address counting means has been used as this means. However, the address counting means provided for each memory plane is expensive, and as the number of memory planes increases, the impact on device cost becomes significant. That is, the conventional magnetic bubble storage device requires a large number of expensive address counting means, and therefore has a defect that significantly increases the device cost. The present invention easily solves the above-mentioned deficiencies, and the magnetic bubble storage device of the present invention has the following features:
As shown in the figure, there are a plurality of memory planes 2 including bubble memory chips 1 and a plane selection attenuator.
means 6 for selectively driving an in-plane magnetic field to each memory plane 2 in response to a memory plane 2; and internal address storage means (BAM) for storing an internal address of the bubble memory chip 1 corresponding to each memory plane 2. 3, receives the internal address information of the memory plane 2 selected by the selective driving means 6 from the internal address storage means 3, increases and decreases it in synchronization with the selective driving means 6, and stores it in the internal address storage means 3. Connected internal address counting means (BAC)
4, and timing generating means (CMP) 5 for providing drive timing to the memory plane 2 based on the external address (BA) and the internal address.

That is, the number of address counting means, which would normally be required in large numbers, was reduced to just one, and a low-cost internal address storage means 3 was introduced instead.

In the device shown in the figure, for example, the number of driving steps of the in-plane magnetic field is counted by the internal address counting means 4 in synchronization with the selective driving means 6 to manage the internal address of the selected memory plane. At the time of switching, the contents of the internal address counting means 4 are written to the address corresponding to the old plane of the internal address storage means 3, and the contents of the address corresponding to the new plane are set to the internal address 5 counting means 4 as an initial value. Alternatively, the number of driving steps of the in-plane magnetic field is counted by the internal address counting means 4 in synchronization with the selective driving means 6, and at the same time, the contents of the address corresponding to the selected memory plane in the internal address storage means 3 are counted. It is also possible to rewrite it sequentially.

Even in this case, when switching memory plane selection, the contents of the address in the internal address storage means 3 corresponding to the new memory plane are set as the initial value of the internal address counting means 4. When the magnetic bubble storage device is configured in this way, all the internal addresses of the internal memory loops in the chip of non-selected memory planes remain in the internal address storage means 3, and only the internal addresses of the selected memory plane are stored in the internal address counting means 4. Placed in and driven. It increases and decreases in synchronization with means 6.

A conventional configuration in which internal address counting means 4 are required as many as the number of memory planes is shown in FIG.
By comprising two internal address counting means and one internal address storage means 3, the device cost does not increase even if the number of planes increases. Although the proportion of the address control circuit portion in the device cost is not so large, if the number of internal address bits becomes, for example, 8 bits and the number of planes becomes about 32, 32 internal address counting means, or 256 bits of internal Address counting means is required, which cannot be ignored in terms of cost.

If these are replaced with one internal address counting means of about 8 bits and one internal address storage means of 256 bits, the overall cost will be the cost of 1 bit of internal address counting means 4 and the cost of random access memory (RAM). ), the latter is overwhelmingly cheaper, at least as far as current IC technology is concerned. As described above, according to the present invention, it is possible to easily solve the defects of the conventional magnetic bubble storage device, which increases the device cost due to the use of a large number of expensive address counting means.

It should be noted that the internal address storage means used in the present invention can be realized within a magnetic bubble memory chip if there is time.

[Brief explanation of the drawing]

The figure is a schematic diagram showing the main parts of the configuration of a magnetic bubble storage device according to the present invention. In the figure, 1 is a bubble memory chip, 2 is a memory plane, 3 is an internal address storage means, 4 is an internal address counting means, 5 is a timing generation means, 6 is a selective driving means for an in-plane magnetic field, and the arrows are Represents the direction in which information flows.

Claims (1)

[Scope of Claims] 1. A plurality of memory planes including bubble memory chips, means for selectively driving an in-plane magnetic field to the memory planes, and internal addresses of memory loops of the bubble memory chips. an internal address storage means for storing a memory plane corresponding to each memory plane; and a memory address selected from the internal address storage means by the selective driving means.
The memory plane includes internal address counting means that receives internal address information of the plane and increases or decreases in synchronization with the selective driving means, and timing generating means that provides driving timing to the memory plane based on the external address and the internal address. A magnetic bubble storage device featuring: 2 The internal address information is stored in the internal address storage means by writing the internal address of the old memory plane managed by the internal address counting means to the corresponding address when switching the selected memory plane between the new and old memory planes. A magnetic bubble storage device according to claim 1. 3. The internal address information is stored in the internal address storage means by sequentially storing the contents of the address of the internal address storage means corresponding to the selected memory plane as the in-plane magnetic field of the selected memory plane is driven. A magnetic bubble storage device according to claim 1, which is performed by rewriting.