JPS594742B2 - Data alignment control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a data alignment control method, in particular, an information bus between an access source device has a bus width of P bytes, and an information bus between a main storage device and a main storage device has a bus width of mP bytes. In a data processing system in which the main storage device has nmP bytes of data read out by one access request, mP byte cross detection means and nmP byte boundary detection means are provided, and the above access The present invention relates to a data alignment control method in which necessary data is aligned and then transferred to a source device.

In a data processing system having a buffer memory, data of, for example, 8 [bytes] x 4 is read out from the main memory by a single access request during so-called block transfer, and is sequentially transferred to the storage controller in units of 8 bytes. On the other hand, from the storage control device to the access source device, 4
Transferred in bytes.

In this case, the access source device issues information such as the start address where the required data is stored, byte length instruction information for the required data, up/down instruction information, etc., and arranges the corresponding data in the desired state. The item will be received in the correct condition.

Note that the data byte length instruction information may be considered to indicate one of 1 byte, 2 bytes, 3 bytes, or 4 bytes in the case of the bus width of 4 bytes. Further, the up/down instruction information may be considered to be an instruction as to whether to go back or forward from the above-mentioned top address position. However, the above system has the following problems. That is, (1) data of a desired byte length required by the access source device may exist across a plurality of 8-byte units sequentially transferred from the main storage device.

In this case, for example, one part of the first 8 bytes transferred and one part of the 8 bytes transferred later are combined, rearranged, and transferred to the access source device. A need arises. (2) In the case of the processing in (1) above, the start address information, byte length instruction information,
It is necessary to ensure that correct alignment is obtained based on the down indication information.

(3) In general, main storage devices are interleaved in order to improve through-foot.

Therefore, in processing (1) above, the order of the data transferred in 8-byte units does not follow the order of the address information and becomes completely random, but it is necessary to perform this process correctly. It is. (4) Furthermore, as mentioned above, 32 bytes (8 [bytes] x 4) can be read from the main memory with one access request, but data of the desired byte length required by the accessing device is above 32
May span byte boundaries.

In this case, it is necessary to make at least two access requests to the main storage device, but if the access source device makes these access requests, the processing becomes extremely complicated. The present invention is aimed at solving the above-mentioned problems, and for example, by providing the above-mentioned 8-byte cross detection means and the above-mentioned 32-byte boundary detection means, it is an object of the present invention to enable the above-mentioned alignment control to be performed correctly. Therefore, the data alignment control method of the present invention can be applied to one or more access source devices, a storage control device that mediates access, and a main device from which NmP bytes of data are read based on one access request. Data processing comprising a storage device, an information bus in MP bytes between the main storage device and the storage control device, and an information bus in P bytes between the storage control device and the access source device. In the system, the predetermined bit information in the address information issued by the access source device and the
MP byte cross detection means for detecting that data to be transferred to the access source device spans a plurality of MP byte units based on the down instruction information and the byte length instruction information; and the NmP byte boundary. a first register in which data in units of MP bytes transferred from the main memory is set;
A second register temporarily saves the contents of the register, and a sorting circuit that rearranges the input data, and reads the contents of the first register based on the detection output of the MP byte cross detection means. The contents set in the first register and the contents of the second register are later led to the alignment circuit, and the detection output of the NrnP byte boundary detection means is Based on this, the storage control device autonomously issues an access request to the main storage device based on the up/down instruction information, and the data to be transferred to the access source device is transmitted to the sorting circuit. This feature is characterized in that the information is read in units of P bytes and then transferred to the access source device. This will be explained below with reference to the drawings. Fig. 1 shows the configuration of an embodiment of a data processing system to which the present invention is applied, Fig. 2 shows an embodiment of information given in response to an access request from an access source device, and Fig. 3 shows arrangement control. FIG. 4 is an explanatory diagram illustrating the problem. FIG. 4 is an explanatory diagram summarizing the 8-byte cross occurrence conditions. FIG. Embodiment configuration, FIG. 6 is an embodiment configuration of an alignment control section according to the present invention, FIG. 7 is an explanatory diagram showing all the gate legs shown in FIG. 6, and FIGS. An explanatory diagram illustrating alignment control using a specific example is shown.

In FIG. 1, 1 is a main memory, 2 is a memory access control circuit, and 3-0 to 3-3 are banks that can be accessed independently from each other and can read, for example, 8 bytes of data at once. , 4 is a storage control device that mediates access processing, and 5 is an order management unit that manages the storage location of 8-byte data transferred from the main storage device 1, that is, address information. Reference numeral 6 denotes a buffer memory, which is generally provided in each central processing unit CPU and is installed in the storage control device 4, 7A, 7B, . . .
. . . represent access source devices, 9 represents an information bus with a bus width of 8 bytes, and 10A and 10B represent information buses each with a bus width of 4 bytes. For example, if the access source device 7A requests an access, If a read access is made to the main storage device 1 as a result of this, the storage control device 4 mediates the access.

That is, the storage device 4 performs processing such as determining the priority order of access requests from other access source devices and checking which banks are accessible, and stores, for example, 1 block, or 8 bytes x 4, from the main storage device 1. Performs processing to read data. Then, for the access source device 7A, the data required by the device 7A is sent to the access source device 7A in 4-byte units.
Please fix the file and transfer it. FIG. 2 shows information used when performing the above reading process. 11 in the figure is address information, bits B8 to B.
3l, ALO is the alignment information that indicates whether or not alignment is possible, and when the logic is "1", the alignment process is executed, and when the logic is (a), the alignment process is not executed.・In the down instruction information, when the logic is "1", it instructs to go back, and when the logic is "river", it instructs to go down backwards.LO, Ll are byte length instruction information, and are "00".
'' indicates a 1-byte length, ``01J'' indicates a 2-byte length, ``10'' indicates a 3-byte length, and ``11'' indicates a 4-byte length. FIG. 3 explains how data transferred from the main storage device 1 in units of 8 bytes is rearranged into a format required by the access source device. That is, the access source device 7A now sets bits B27 to B3l as address information "0001".
0'', information ALl is a logical river, information LO, L
If l is accessed with the value "10", main memory 1
When 8 bytes including bytes A, B, and C shown in FIG. 3 are transferred from , the 4 bytes in the shaded area starting with byte A can be extracted and transferred to the access source device 7A. However, now the bits B27 to B3l are "011".
10'', information ALl is logical ``1'', information LO, L
When l is accessed with the value ``11J'', the desired 4 bytes D, E, F are transferred from the 8 bytes including the 8 bytes F and G including the byte NE shown in FIG.
, G must be properly aligned and transferred to the access source device 7A. Also, for bits B27 to B3l,
10001'', information ALl is logic D'', information LO
, Ll is accessed with the value [11], the desired 4 bytes D, E, F, and G are similarly arranged from the 8 bytes including bytes F and G and the 8 nodes including bytes D and E. It is necessary to correct the data and transfer it to the access source device 7A.
Furthermore, "11110" is given to bits B27 to B3l, information ALl is set to logic "1", and information LO and Ll are set to the value "11".
1, the 8 bytes including bytes H and I shown in FIG. It is necessary to assemble bytes H, I, J, and K from the 8 bytes including bytes J and K shown in FIG. Also, when bits B27 to B3l are given "00001U", information ALl is set to logic "O", information LO and Ll are accessed with value "11", two access requests are issued in the same way, and byte H, It is necessary to put I, J, and K together. Therefore, in the case of the present invention, the data of the data length required by the access source device is, for example, D, E, F, G.
A d-byte cross detection means for detecting whether or not a d-byte cross is detected across multiple 8-byte boundaries such as 1, J, and K; N to detect whether multiple access requests are required
mP byte boundary detection means is provided to perform the above alignment control. Figure 4 shows D, E shown in Figure 3,
7 is a diagram summarizing the manner in which the 8-byte cross state occurs, that is, 8-byte units such as F, G, H, I, J, and K are spread across a plurality of 8-byte units. B29 to B3l, A in the diagram
LO, Al, l, LO, Ll correspond to FIG.
Also, the * mark indicates that the logic can be either "O" or "1", and 00 means that the information LO, Ll is "00".
It means that it is not. An 8-byte cross does not occur in any case other than the mode shown in FIG. The 8-byte Talos detection circuit, which will be described later with reference to FIG. 5, detects the occurrence of the aspect shown in FIG. FIG. 5 shows the configuration of an embodiment of the autonomous access request control section according to the present invention. Code 11 in the figure, b8 to B3l, ALO, ALl
, LO, and Ll correspond to FIG. 2, 12 is an 8-byte cross detection circuit, 13 is a 32-byte boundary detection circuit, and 14 is a dynamic address translation circuit that converts a given logical address into a physical address. 15 is a memory address register, 16 is an adder that adds -4 to address information bits B8 to B3l, 17 is an adder that adds +4 to address information bits B8 to B3l, 18 and 19 each represent an AND circuit. The 8-byte cross detection circuit 12 detects the occurrence of the mode shown in FIG.
1” is emitted.

In addition, in the 32-byte boundary detection circuit 13, the state in which the AND circuit 18 is turned on means that the byte K shown in FIG. corresponds to the condition. Therefore, the adder 16 adds -4 to the address information given with bits B8 to B3l and supplies the result to the dynamic address translation circuit section 14. Further, the state in which the AND circuit 19 is turned on is the state in which the AND circuit 19 is turned on.
The illustrated byte H is designated by the head address information and corresponds to a state where bytes H, , J, and K straddle a 32-byte boundary. Therefore, the adder 17
+4 is added to the address information given with 8 to B3l and the result is led to the dynamic address translation circuit section 14. That is, the configuration shown in FIG. 5 represents a configuration in which the storage control device 4 autonomously issues an access request. FIG. 6 shows the configuration of an embodiment of the alignment control section according to the present invention. Reference numerals 20-E and 200 in the figure are first registers according to the present invention, 21 is a second register according to the present invention, 22 is an alignment circuit, 23 is a leg of the alignment circuit Fbl, and G1 to G6 are respective gates. It represents. Each of the gates G1 to G6 is turned on under the conditions shown in FIG. 7, respectively. Note that, as described above, in the case of the present invention, the main storage device 1 is interleaved. For this reason, the 8-byte unit information transferred via the information bus 9 (Fig.
Information in bytes does not necessarily arrive in order. This order is managed by an order management section 5 shown in FIG. The signals indicated as (inverted) in FIG. 7 may be considered to be logic "1" when the above order is reversed. As can be seen with reference to FIG. 7, for example, gate G1 is activated when (l) an 8-byte cross occurs and bit B29 is logic "1", or (Ii) when the above inverted signal is asserted and bit B29 is is turned on when the logic is "1", and the data set in the register 20-0 is saved into the second register 21. FIGS. 8A to 8D show explanatory diagrams specifically explaining the alignment control according to the present invention. The symbols in the figure correspond to those in FIG. Now, as shown in FIG. 8A, bits B27 to B3l in the address information are "01110".
”, information ALO indicates logic “1”, information AL1 indicates logic “1”, and information LO, L1 indicates value “11”, the data required by the access source device is the 8th The 4 bytes are indicated by diagonal lines in Figure B. At this time, bits B27 and b28 from the main storage device 1 are set to “00”.
, "01", "10", and "11", each 8-byte unit of information is randomly transferred. FIG. 8C shows a process in which 8-byte information including bytes F and G is transferred earlier than information including bytes D and E. In addition, in FIG. 8D, the reverse, that is, the inverted signal is logic "0".
] represents the processing in the case of a normal ranking. In the case shown in FIG. 8C, as is clear from FIG. 7, gate G2 is turned on to save information including bytes F) and G to the second register 21. Next, part-time jobs D and E for the second time.
When the information containing the information is set in the first registers 20-E and 2O-0, gates G3 and G6 are turned on. That is, bytes F and G and bytes D and E are led to the alignment circuit 22. In the sorting circuit 22, the data is sorted as shown by the arrow in the figure, and transferred as bytes D, E, F, and G to the access source device. In addition, in the case shown in FIG. 8D, the gate G1 is used to save information including bytes D and E to the second register 21.
Turn on. Then, when the information including bytes F and G is set in the first registers 20-E and 2O-0 for the second time, gates G4 and G5 are turned on. That is, byte F,
G and bytes D and E are led to an alignment circuit 22. In the alignment circuit 22, the alignment is similarly adjusted.
Transferred to the access source device as bytes D, E, F, and G. Note that the access source device is the bytes A, B, and
If you need data such as C, an 8-byte cross condition will not occur. Therefore, as is clear from No. 7, when information in units of 8 bytes including bytes A, B, and C is set in registers 20-E and 20-0, gates G4 and G6 are turned on and the data is immediately aligned. Needless to say, it is guided to the circuit 22. As described above, according to the present invention, it is possible to correctly align and mount the data according to the data required by the access source device and then transfer the data to the access source device.

Furthermore, even if it becomes necessary to issue multiple access requests to the main storage device, the access source device is not involved at all, and the storage control device autonomously issues the access requests. That is, all the problems mentioned at the beginning of this specification are solved.

[Brief explanation of drawings]

Fig. 1 shows the configuration of an embodiment of a data processing system to which the present invention is applied, Fig. 2 shows an embodiment of information given in response to an access request from an access source device, and Fig. 3 shows arrangement control. An explanatory diagram explaining the problem, FIG. 4 is an explanatory diagram summarizing the 8-byte cross occurrence conditions, and FIG. 5 is an implementation of the autonomous access request control unit according to the present invention provided in the storage control device. Example configuration, FIG. 6 is an example configuration of an alignment control section according to the present invention, FIG. 7 is an explanatory diagram collectively representing each gate control shown in FIG. 6, and FIGS. 8A to D
shows an explanatory diagram illustrating alignment control according to the present invention using a specific example. In the figure, 1 is a main storage device, 4 is a storage control device, 7 is an access source device, 5 is a sequence management unit, 9 and 10 are information buses, and B8
or B3l is address information, ALl is up/down instruction information, LO, Ll is byte length instruction information, 12 is MP
Byte cross detection means; 13 is NmP byte boundary detection means; 20 is a first register; 21 is a second register;
22 represents an alignment circuit.

Claims (1)

[Claims] 1. Provided for one or more access source devices, a storage control device that mediates access, and a main storage device from which nmP bytes of data are read based on one access request. , in a data processing system having an information bus in units of mP bytes between the main storage device and the storage control device, and an information bus in units of P bytes between the storage control device and the access source device; The data to be transferred to the access source device is determined based on the predetermined bit information, up/down instruction information, and byte length instruction information in the address information issued by the access source device.
mP byte cross detection means for detecting spanning over a plurality of P byte units and nmP byte boundary detection means for detecting spanning across the nmP byte boundary, A first register in which data in units of mP bytes to be received is set, a second register in which the contents of the first register are temporarily saved, and a sorting circuit for rearranging the input data are provided. The contents of the first register are saved in the second register based on the detection output of the cross detection means, and the contents set in the first register and the contents of the second register are later transferred to the second register. Further, based on the detection output of the nmP byte boundary detection means, the storage control device autonomously requests access to the main storage device based on the up/down instruction information. At the same time, the data to be transferred to the Aquias source device is transmitted to the P by the alignment circuit.
A data alignment control method characterized in that the data is arranged in byte units and then transferred to the access source device. 2 The main memory device stores mP bytes of data.
The storage control device is configured to transfer address information in units of P bytes regardless of the order of address information, and has an address order check function for checking address information corresponding to the transferred data in units of mP bytes, 2. A data sorting control system according to claim 1, wherein a data input route leading to said sorting circuit is controlled based on a rank inversion output from a check function.