JPS6052455B2 - Parity detection function check method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a parity detection function checking method that can simultaneously check a plurality of parity detection functions in a channel device connected to a main processing unit by a common bus.

In a channel device connected to a main processing device by a common bus, a channel device is used that has a built-in subprocessing device that controls the decoding and execution of instructions. I have also become able to manage myself.

As one method of self-management, a method has been adopted in which the sub-processing device intentionally generates a parity error in a parity detection circuit that detects a parity error on the common bus, and then checks its functional operation. Conventionally, when a plurality of parity detection circuits are present in a cultural channel device, it has been necessary for the sub-processing device to generate a parity error for each parity detection circuit. The present invention has been made to solve the above-mentioned inconvenience, and aims to provide a parity detection function checking method that can check the detection functions of a plurality of parity detection circuits by setting one error condition.

The present invention provides a channel device that is connected to a main processing device and a main storage device by a common bus, and that includes a built-in subprocessing device that controls data transfer between the main storage device and the file device.
a first parity detection circuit for detecting a parity error in an input signal from the common bus; and a second parity detection circuit for detecting a parity error in an output signal from the channel device to the common bus; A parity detection function characterized in that the device can simultaneously check the parity detection functions of the first and second parity detection circuits by setting one error condition that causes a parity error to occur in the transferred data. This is a check method.

Note that the present invention can also simultaneously check the detection functions of a plurality of parity detection circuits provided along the circuit through which data flows. Generally, in order to check the parity detection function of a parity detection circuit, a parity error state is intentionally caused in the data to be checked. A bit position is required in a predetermined register, and a circuit (exclusive OR circuit) for causing polarity reversal is also required. Therefore, as the number of parity detection circuits to be checked increases, the advantage of the present invention is that the number of registers and exclusive ORs required increases in comparison. , only one set of the register and the exclusive OR circuit is required, and the number of steps executed by the sub-processing unit is also reduced, which has the advantage of minimizing both hardware and software. The present invention will be explained below with reference to the drawings.

The drawings are block diagrams for explaining one embodiment of the present invention.
1 is the main processing unit, 2 is the main storage unit, 3 is the sub-processing unit, 4
is a bus driver, C is a latch circuit, 5 is a bus receiver, 6 is a register, 7 is an EOR circuit, 8 and 9 are parity detection circuits, 10 is a buffer memory I8, 11 is a control circuit,
12 is a disk device, 13 is a channel device, C is a common bus, D and D'' are data, E is a parity error signal, and p is an instruction bit. In this embodiment, the channel device 13 has two parity detection circuits. In addition, the buffer memory 10 in the drawing is a first-in, first-out system WIF.
O memory. In the drawing, first the disk device 12
In the case of writing data to the main storage device 2, data D from the main memory device 2 is stored in the buffer memory 10 via the common bus C1 bus receiver 5 and the EOR circuit 7, and then stored in the buffer memory 10.
The data is latched in a latch circuit (not shown) inside and transferred to the disk device 12. On the other hand, in the case of reading data, data D'' from the disk device 12 passes through the latch circuit of the control circuit 11, is stored in the buffer memory 10, is read out again, is latched in the latch circuit C, and is latched in the bus driver 4. The data is stored in the main memory device 2 via the common bus C. The above is the normal circuit operation. In the drawing, parity detection circuits 8 and 9 are provided on the input and output sides of the buffer memory 10, respectively. The processing device 3
When checking the detection functions of these two parity detection circuits, the instruction bit p in the register 6 is set to a signal "1". Therefore, on the output side of the EOR (exclusive OR) circuit 7, the data is converted into data including a parity error, and this data is stored in the buffer memory 10. At this time, the parity detection circuit 8 detects the parity error,
A parity error signal E is generated. By detecting this parity error signal E (not shown) by the sub-processing device 3, it is possible to confirm whether the detection function is normal. Next, when the sub-processing device 3 reads out the data (including parity errors) stored in the buffer memory 10 to the latch circuit 4'', a parity error is detected by the parity detection circuit 9 and a parity error signal E is generated. As described above, the detection functions of the two validity detection circuits 8 and 9 provided along the bus (or circuit) through which data flows are controlled by setting a signal to the instruction bit p of the register 6 and This can be checked simultaneously with the EOR circuit.

It goes without saying that the register 6 can be set as a register in the sub-processing device 3 or as a register in a memory area.

[Brief explanation of drawings]

The drawings are block diagrams for explaining one embodiment of the present invention.
The symbols used in the figure are as follows. 1...Main processing unit, 2...Main storage device, 3...Sub-processing unit, 4...Bus driver, 5...Bus receiver , 6...Register, 7...EOR circuit, 8, 9...
Parity detection circuit, 10... buffer memory,
11...Control circuit, 12...Disk device, 13...Channel device, C...Common bus, D, D''...Data, E: Parity error signal, p is an instruction bit.

Claims (1)

[Claims] 1 connected to the main storage device by a common bus, the main storage device;
a sub-processing device that controls data transfer between file devices;
a buffer memory provided in the middle of the data transfer route and storing data from the main storage device and the file device;
a first parity detection circuit for detecting a parity error in data supplied from the main memory to the buffer memory; a register for storing data transferred from the buffer memory to the main memory; and a second parity detection circuit for detecting a parity error in the data supplied from the common bus to the buffer memory, the channel device comprising an exclusive OR circuit having a function of causing a parity error in the data supplied from the common bus to the buffer memory. The sub-processing device causes data including a parity error to appear on the output side of the exclusive OR circuit and stores it in a buffer memory, checks the detection function of the first parity detection circuit, and A method for checking a parity detection function, characterized in that the readout function of the second parity detection circuit is checked by reading the information into the register.