JPS5948401B2 - Sequence control device - Google Patents

Description

[Detailed description of the invention] The present invention relates to a sequence control device.

Conventional devices of this type are provided with a program memory such as a diode matrix, and are configured so that the contents of the memory can be changed by attaching and detaching the program memory from the main body.

However, in conventional devices, if the program memory is extracted while the program is in progress, all input and output are turned off.
Even if you want to change the program midway through the program, you can only do so when the entire program is completed. In order to solve these drawbacks, the following can be considered. That is, in FIGS. 1 and 2, 1 is a main body formed in the shape of a rectangular parallelepiped, and a stop operation switch 2 and a plurality of light emitting diodes 3 are provided on one front side of the main body 1, and a plurality of light emitting diodes 3 are provided below. An output relay box 5 is formed in which an output relay 4 is provided, and the output relay box 5 has a tongue-shaped connecting portion 6 connected to a connector (not shown) at the upper part of the output relay box 5.
A program memory T consisting of a c-board is provided in a removable manner. This program memory 7 has a built-in diode matrix, and a predetermined program can be arbitrarily set using diode pins (not shown). Further, in the main body 1, a plurality of PC boards configuring circuits such as a control section and an input/output section are provided and connected to the program memory T. Then, the main body 1
An input terminal 8 and an output terminal 9 are connected to the back side of the unit, and external circuits such as a power supply 10 and a load 11 are connected to the output terminal 9. The input buffer 13 to which the input switch 12 is connected is connected to the program memory 7 via a latch circuit 14, and the program memory 7 is connected to the output transistor 16 via a latch circuit 15.

The collector of this output transistor 16 and the supply power terminal I
A relay contact 1 connected to the output terminal 9 is connected between the
An output relay 4 that controls 8 is connected. Then,
The latch circuit 14 is connected to the output side of an AND gate 23 whose input sides are connected to a terminal 21 to which an input read signal is applied and a terminal 22 to which a stop signal from the stop operation switch 2 is applied.

The latch circuit 15 also has an AN terminal connected to the input side of the terminal 24 to which the output read signal is applied and the terminal 22.
The output side of D gate 25 is connected. Further, the terminal 22 is connected via an inverter 26 to an AND gate 27 which is multiplied by a control signal.
is connected to a control circuit 28 that performs addressing. In such a configuration, normally no stop signal is output, so when the input switch 12 turns 0N, the output relay 4 operates according to the program set in the program memory 7, turning the relay contact 18 from 0N to 0FF. It performs sequential operations.

At this time, a control signal also enters the control circuit 28 to specify the address. To change the program after a certain point during normal operation,
It is necessary to stop the program progress and change the contents of the program memory 7, but in such a case, the stop operation switch 2 is turned ON. As a result, when the next input read signal and output read signal are received, AND gates 23 and 27 open and latch the latch circuits 14 and 15, respectively. At the same time, the operation of the control circuit 28 is also prohibited. As a result, no matter how the state between the latch circuits 14 and 15 changes, there will be no change in the input/output, and even if the program memory 7 is removed, its contents are changed, and then reinserted, the previous stage remains unchanged. The input/output status of is maintained. Therefore, when the stop operation switch 2 is turned OFF, the stop signal is canceled again, the latch circuits 14 and 15 are released, and the work is carried out according to the changed program from the middle. However, with such a structure, if you forget to operate the stop operation switch 2, the program memory 7
The first object of the present invention is to provide a sequence control device that automatically generates a stop signal to maintain input and output simply by extracting the program memory. It is.

A second object of the present invention is to provide a sequence control device that can display the state in which a stop signal is being output.

Next, a first embodiment of the present invention will be described based on FIGS. 3 and 4.

Components that are the same as those described in FIGS. 1 and 2 are designated by the same reference numerals, and explanations thereof will be omitted. In this embodiment, terminal 2 for a stop signal is connected to AND gates 23 and 25.
2 through the 0R gate 29, and this 0R gate 2
An AND gate 30 is connected to the input side of 9.
Two power supply terminals 33 and 34 are connected to the input side of this AND gate 30 via resistors 31 and 32, and these power supply terminals 33 and 34 are also connected to a connector 35 and are connected to this connector 35. The program memory 7 that is inserted has two shorting wires 36 that serve as a signal generator.
, 37, and one terminal of the connector 35 is grounded. In such a configuration, if the program memory 7 is inserted, the AND gate 30
is closed, and the operation in this state is exactly the same as in the previous embodiment.

Therefore, when the program memory 7 is pulled out while the program is in progress, the short circuit lines 36 and 37 formed in the program memory 7 disappear, and the AND gate 30 opens. As a result, a stop signal similar to that when the stop operation switch 2 is operated is automatically applied to the AND gates 23 and 25, and the latch circuits 14 and 15 are latched. Therefore, the stop signal is automatically generated by simply pulling out the program memory 7 without having to operate the stop operation switch 2, and the input/output is maintained. Next, a second embodiment of the present invention will be explained based on FIG.

Although the explanation of the electric circuit is omitted, both ends of the connection part 6 of the program memory 7 are connected by a shorting wire 38 which becomes a signal generation part, and one of the corresponding connectors 35 is grounded and the other is connected through a resistor 39. A power supply terminal 40 is connected thereto, and a stop signal terminal 41 is also connected thereto. Therefore, when the program memory 7 is pulled out, a stop signal is generated, and when it is connected to the connector 35, the stop signal disappears. Furthermore, what is shown in FIG. 6 is a third embodiment of the present invention, and this embodiment is different from the one shown in FIG. A light emitting diode 42 serving as a section is provided.

Moreover, the one shown in FIG. T is a modification example in which a light emitting diode 42 is turned on or off via a transistor 43. Since the present invention is configured as described above, a signal generating section is provided at the connection part of the program memory, so that a stop signal can be automatically obtained by simply pulling out the program memory. By applying a stop signal, the latch circuits provided on the input and output sides of the program memory are latched, so that even if the program memory is pulled out, the previous input/output state can be maintained. It is possible to freely change the program midway through the program, and if a display section is provided in the circuit, it can be determined whether the program memory is set or not from the outside. It is.

[Brief explanation of the drawing]

Fig. 1 is an exploded perspective view showing one example of holding input/output, Fig. 2 is an electric circuit diagram thereof, Fig. 3 is an electric circuit diagram showing the first embodiment of the present invention, and Fig. 4 is its electric circuit diagram. A plan view of the main parts, FIG. 5 is a plan view showing the second embodiment of the invention, FIG. 6 is a plan view showing the third embodiment of the invention, and FIG. 1 is a plan view showing a modification thereof. It is a diagram. 6... Connection section, T... Program memory, 14, 15... Latch circuit, 36, 3?
, 38... Short circuit line (signal generation section), 42...
...Light emitting diode (display part).

Claims (1)

[Scope of Claims] 1. A latch circuit is provided on the input side and the output side of a removable program memory to inhibit input and output by a stop signal, and when the program memory is extracted from a connecting portion of the program memory, the stop signal is removed. A sequence control device comprising a signal generation section that generates a signal. 2 A latch circuit is provided on the input side and the output side of the removable program memory to inhibit input and output by a stop signal, and a signal is generated that generates the stop signal when the program memory is extracted from the connecting portion of the program memory. What is claimed is: 1. A sequence control device characterized in that a display unit is connected to the signal generating unit to indicate whether or not a stop signal is being output.