JPS5948476B2 - Direct memory access method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a direct memory access (hereinafter referred to as DMA) method in which data is accessed to a memory combined with a processor without going through the processor.

Such DMA is a means mainly used when data is transferred at high speed from a memory attached to a processor to a peripheral device.

In this case, the memory in which the data is stored is addressed independently of the processor, so generally D
During the MA execution period, the operation of the processor is stopped and the address bus and data bus are disconnected from the memory. Therefore, in a system configuration where dynamic memory that requires refreshing is used as part of the memory and the processor refreshes this memory, there is a risk that data stored in the dynamic memory may be lost during DMA execution. In order to prevent this, a circuit other than the processor must continue refreshing the dynamic memory even during DMA execution.

On the other hand, while the processor is processing data, the memory is connected to the processor, and refresh must be performed when no data is exchanged between the processor and the memory. Since then, it has become effective to use a processor with a refresh function in terms of simplifying the system configuration.

Therefore, in systems that perform DMA, conventionally the refresh function during the DMA period has been switched from the processor to an external circuit, or a refresh-only circuit has been provided separately from the processor. This had the disadvantage of complicating the system configuration.

The present invention has the purpose of eliminating such drawbacks of the conventional art, and
The amount of data transferred at one time by MA is relatively small; for example, about IK bytes is often sufficient.

Focusing on this, we used static memory as the memory area for DMA execution, dynamic memory for other memory areas, and
In MA, the processor and static memory are separated, and the refresh operation of the dynamics memory by the processor is continued, thereby providing a direct memory access method that greatly simplifies the system configuration. The details of the present invention will be explained below with reference to block diagrams showing embodiments.

In the figure, a processor 1 such as a microprocessor is
Volatile RAM (RandomAccessMemo
ry) and a static memory 3 using non-volatile RAM, between which there is an address bus 4A for transmitting addressing signals and a data bus 4A for transmitting data signals. A gate 7 is connected to the static memory 3 by a bus 5A.
A gate circuit 7 consisting of A to 7C is inserted.

The processor 1 also includes an interrupt terminal 1A to which a DMA start interrupt signal and a DMA end interrupt signal are applied at the start and end of a DMA operation, and a response terminal 1B to send out response signals to these interrupt signals. Prepared, DMA
It is programmed to stop general data processing operations based on the main program in response to a start interrupt signal, and to execute only a specific program including a refresh operation.

Note that the gate circuit 7 is normally on, and in normal operation, the processor 1 exchanges data with the dynamic memory 2 and the static memory 3, executes predetermined data processing, and performs dynamic processing. A refresh operation for the micro memory 2 is also performed.

A static memory 3 is used as a memory area for DMA, and a dynamic memory 2 is used for other memory areas. Now, assuming that the terminal device 6 such as a cathode ray tube input/output device needs to execute DMA, the switch SW1 such as a mechanical contact switch or a semiconductor switch circuit is turned on, and the power supply ■ is turned on via the resistor 8. In order to ground the given point A, the A point becomes "L" (low level (c)), and the output of the AND gate 9 changes to "L", which turns off the gate circuit 7 and turns off the static state. Address bus 4 on memory 3 side
B and data bus 5B are separated from processor 1.

At this time, however, the dynamic memory 2 remains connected to the processor 1. When the point A reaches 8L1, a charging current passes from the power supply 1 to the capacitor 11A via the resistor 10A, which turns on the transistor 12A, increasing the terminal voltage of the resistor 13A to ゛H゛゜ (high level). ), this signal is applied to the inverter 15 via the loop prevention diode 14A, and a pulse signal of 6L'' is sent to the interrupt terminal 1A of the processor 1 as an interrupt start signal. "L1" is converted to "H0" by the inverter 16 and is applied to a first instruction circuit 17A using a code generator or the like, whereby the circuit 17A generates a DMA start interrupt instruction to be described later.

When the processor 1 receives an interrupt signal, it sends a response signal from the response terminal 1B, so this signal turns on the gate circuit 18, and sends the interrupt command from the first instruction circuit 17A to the data bus 5A. This command is given to processor 1. Processor 1 then stops the data processing operation by the main program, but dynamic memory 2
A refresh operation for 2000 will result in a continuous interrupt state.

On the other hand, the response signal from the response terminal 1B drives the clock input CK of the flip-flop circuit (hereinafter referred to as FFC) 19, and at this time, since the input J is "H1" and the input K is "1L",
Output Q becomes 6H - Output Q becomes 6L'', AND gate 2
The output of 0 changes to 6H7 and drives the pulse generator 21 to start generating DMA clock pulses.

This clock pulse is counted by the counter 22, and the count output of the counter 22 is given to the static memory 3 as an address designation signal, and the clock pulse is also given to the latch circuit 23 as a strobe signal. The data read from is held in the latch circuit 23 in synchronization with address designation, and its contents are sequentially sent to the terminal device 6.

The above results in a DMA operation, but in this interrupt state, the processor 1 is executing a specific program that does not use the static memory 3, so that the refresh operation for the dynamic memory 2 is continued.

Although a specific program can be set arbitrarily, if the static memory 3 is used as a so-called video memory and the contents of the same memory 3 are to be displayed on a cathode ray tube or the like, D
To allow the starting point of MA to occur at any step in the main program that performs general data processing, it is generally
It is preferable to set it in the ALT state.

Therefore, at the end of DMA, it is necessary to take the processor 1 out of the HALT state, and the next operation is performed by turning off the switch SW1.

That is, when the switch SW1 is turned off and the A point returns to 6H1, the output of the inverter 16 becomes "L", thereby the output of the AND gate 20 also changes to "L1", and the operation of the pulse generator 21 is stopped. , the reading of data from the static memory 3 by the counter 22 and the latch circuit 23 is completed. On the other hand, when point A becomes 6H1, capacitor 11B is charged via resistor 10B,
The transistor 12B is turned on by the terminal voltage of the resistor 10B, and the terminal voltage of the resistor 13B is set to 6H'', which is applied to the input of the inverter 15 via the diode 14B, and the output is set to ``L1'' and sent to the interrupt terminal 1A, ending the DMA. At the same time as sending an interrupt signal, 6H at point A drives the second instruction circuit 17B, which is similar to the first instruction circuit 17A, and the DM
An A end interrupt command is generated and applied to the processor 1 via the gate circuit 18 and data bus 5A.

The processor 1 is released from the HALT state by the DMA end interrupt command, and in order to send out a response signal again from the response terminal 1B, the FFC 19 is driven, and this time, the input J is set to 6.
Since L7 and input K are 6H1, FFC・19
is inverted, and the output Q becomes 6L'' and the output Q becomes 6H''.

Then, the output of the AND gate 9 changes to 6H1, and in order to return the gate circuit 7 to the on state, the static memory 3 is connected to the processor 1 again, returning to the state before the start of DMA.

Note that the above-mentioned first and second instruction circuits 17A, 17B
The command sent from the processor 1 is a commercially available μPD.
When using the 780, it is preferable to use one that calls the subroutine programs shown in the table below.

That is, the DMA start program first starts with EI (Ena
ble Interrupt. ) to enable interrupts, HALT to stop all operations except the refresh operation, and RETI (RETurn from
Interrupt. ) to prepare the return from the interrupt state to the main program execution, and in the DMA termination program, in order to allow time to elapse until the gate circuit 7 returns to the on state, first the NOP (NoOPera)
After one machine cycle has elapsed due to
In addition to enabling interrupts using EI, RETI causes a transition to the RETI of the interrupt initiation program, and returns to execution of the main program.

Although each of the above-mentioned programs is selected depending on the type of processor 1, each program generally only requires about 3 bytes.

Further, the circuits of the transistors 12A and 12B that generate the DMA start interrupt signal and the DMA end interrupt signal may use a pulse generation circuit such as a monostable multivibrator, and the first and second instruction circuits 17A and 17B as one,
The same effect can be achieved even if each instruction is generated by switching, and by adding some circuits, the terminal device 6 can be generated during DMA execution.
The illustrated circuit configuration has various flexibility, such as being able to write data into the static memory 3 from the beginning.

Note that any device or circuit that requires DMA can be used as the terminal device 6.

As is clear from the above explanation, according to the present invention, DM
Since the refresh operation by the processor continues even while A is being executed, there is no need to provide a separate refresh circuit, and the configuration is extremely simplified.
The start and DMA end programs only need to be about 3 bytes, so no particularly complicated programming is required, and the invention is highly effective in various data processing systems that require DMA operations.

[Brief explanation of the drawing]

The figure is a block diagram showing an embodiment of the present invention. 1...Processor, 2...Dynamic memory, 3...Static memory, 4A,
4B...Address bus, 5A, 5B...
・Data bus, 7... Gate circuit.

Claims (1)

[Claims] 1. In a data processing system equipped with a processor having a refresh function for dynamic memory,
Static memory is used as a memory area for executing direct memory access, the dynamic memory is used for other memory areas, and only the processor and static memory are separated during the direct memory access. . A direct memory access method, characterized in that the processor continues a refresh operation on the dynamic memory.