JPH0432422B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a program loading method, and in particular to constructing a multiprocessor system having a dedicated subprocessor for controlling I/O devices and communication lines in addition to a main processor. The present invention relates to a method for loading a control program into a subprocessor block in a computer system that uses a subprocessor block.

Description of the Prior Art In general, the control program on the subprocessor block side is stored in a ROM and fixedly incorporated as H/W, or it is loaded from the main block side at initial startup. In the former case
The latter method is generally used because it depends on the capacity of the ROM, increases the amount of H/W, and has poor expandability in terms of system control.

However, in the latter case, since the memory block of the subprocessor into which the control program is loaded is connected to the system bus, a control circuit just for loading the program is required, and an increase in the amount of H/W can be avoided. Unable to do so.
The disadvantage was that load control was also complicated.

OBJECTS OF THE INVENTION The present invention has been made in order to eliminate the above-mentioned drawbacks of the conventional technology.Therefore, an object of the present invention is to enable the main processor to directly control the system clock of the sub-processor and to load the control program of the sub-processor. By using the address sent out in the instruction fetch cycle of the sub-processor as the load address without giving it from the main processor, the amount of configuration of the interface control circuit between the sub-processor and the main processor can be reduced. The purpose of this invention is to provide a simple method for load control.

Composition of the Invention In order to achieve the above object, the program loading method according to the present invention provides load control from the main processor side to a memory block storing a program for controlling the sub-processors in a multi-processor system having sub-processors. The main processor directly controls the system clock of the subprocessor, gives the address sent out in the instruction fetch cycle of the subprocessor as a load address, and writes the load data in the gap between the execution cycle and the execution cycle.

Principle and Operation of the Invention Normally, the state of a processor is divided into an instruction fetch cycle and an execution cycle.
Each cycle operates in synchronization with the system clock input to the processor, and at this time, once the clock is stopped (fixed input), the state immediately before that point is maintained. Therefore, if the clock is stopped during an instruction fetch cycle, the address at that time remains pointing to the fetch address, while in the execution cycle a NOP (No
operation), the next fetch address will point to the incremented address.

DESCRIPTION OF EMBODIMENTS OF THE INVENTION Next, a preferred embodiment of the present invention will be specifically described with reference to the drawings.

FIG. 1 shows one embodiment of the present invention, and is a block diagram of a sub-processor, which is the main focus of the present invention, a memory section in which its program is stored, and a system bus. In the figure, reference number 1 indicates a system bus, and the system bus 1 includes a bus control section 2 that inputs data signals and controls their switching, and an I/O bus that provides a reset input to the subprocessor 7 and is connected to the clock control section 3. An O decoder 8 is connected. The clock for the sub-processor 7 is supplied from the clock generator 5 during normal operation, and when a program is loaded, an ON/OFF transition signal generated by an I/O command from the main side is supplied as the clock.

FIGS. 2a to 2e are tying charts for explaining the features of the loading method according to the present invention. However, depending on the type of subprocessor 7, several clock cycles are required between the instruction fetch cycle and the execution cycle, but for the sake of clarity, it is assumed that the state of the processor changes in one cycle each. If the clock ON (or OFF) state is maintained, the state of the processor will not change and will remain in the maintained state. The main processor 10 performs an operation to stop the internal operation of the sub-processor 7 by repeatedly inputting a clock (input) signal 9 that drives the operation of the sub-processor 7 and keeping it at an ON (or OFF) level. By stopping the operation immediately after entering the instruction fetch cycle, the processor state and output state are maintained at the state of the instruction fetch cycle.

To explain the present invention in more detail, first, in order to initialize the sub-processor 7, the reset signal 4 is turned "ON" by an I/O command from the main processor 10 side, and the system clock 9 of the sub-processor 7 is turned on by the main processor. It is switched to a transition signal based on an I/O command from the setter 10 and is set as an "ON" input.

In this state, the subprocessor 7 enters the first fetch cycle, and the fetch address to the memory 6 indicates address 0. Here, the main processor 10 sends a write signal and the NOP code to the sub-processor 7 to write the NOP code to address 0 of the memory 6. Next, when the subprocessor system clock is turned OFF, the subprocessor 7 takes in the memory contents indicated by the fetch address and keeps the address at 0 until the next execution cycle begins. At this time, if the main processor 10 also sends the first data to be loaded together with a write signal, that data will be newly written to address 0.

Here, when the system clock 9 is turned ON and the execution cycle begins, the subprocessor 7 takes in NOP as an instruction code, so it does not give any operation to the outside and is executed by the clock transition. The next instruction is fetish. In this case, the fetch address is incremented by +1 from the previous fetch address to point to address 1. Then, by repeating the above processing in this state, the loading is completed.

To transfer control to the loaded program, the subprocessor 7 is reset again to start at address 0. However, the clock 9 to the subprocessor 7 is set to the basic clock input mode from the system clock generator 5.

Effects of the Invention As explained above, according to the present invention, by using the address from the sub-processor as the load address through clock control of the sub-processor, there is no need for direct address control from the main processor. , a simple interface can be configured.

[Brief explanation of drawings]

FIG. 1 is a block diagram partially showing an embodiment of the present invention. 1...System bus (S-BUS), 2...Data bus control unit (DBC), 3...Clock control unit (CLKC), 4...Reset signal (Reset), 5...System clock generator (OSC), 6... Memory (MEMO), 7...Subprocessor (SCPU), 8...
I/O decoder (D), 9...system clock (S-CLK), 10...main processor. FIG. 2 is a timing chart for explaining the present invention. a...Reset signal 4, b...Subprocessor state cycle (F: instruction fetch cycle, E: execution cycle), c...Subprocessor system clock 9, d...Subprocessor output address, e...Memory write data (NOP) : No operation code, D1, D2: Load data).

Claims (1)

[Scope of Claims] 1. In a computer constituting a multiprocessor system having a dedicated subprocessor for I/O devices, communication control, etc., the subprocessor has a memory to store a program for controlling it. And the main processor is
The system clock of the sub-processor is directly controlled through an I/O decoder and a clock control section, and the address sent out in the instruction fetch cycle of the sub-processor is given as the load address of the memory, and the following (1) is carried out. A method for loading a program into a subprocessor system, characterized in that the program is loaded between an instruction fetch cycle and an execution cycle according to the steps shown in (6). (1) Resetting the subprocessor from the main processor (2) Putting the subprocessor into an instruction fetch cycle by controlling the subprocessor's clock (3) During the instruction fetch cycle in (2) Then, write the NOP code from the main processor to the address specified by the subprocessor (4) Control the clock and write the NOP code to the subprocessor.
Fetch the instruction fetch cycle of the subprocessor, and then write the load data from the main processor to the above address specified by the subprocessor (5) Control the clock, set the subprocessor as an execution cycle, and execute NOP. and increment the address (6) Repeat steps (2) to (5) above.