JPS5948568B2 - flip-flop circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a completely new reset-priority flip-flop circuit, which is implemented in CMOS so that it can be operated at low voltage and low power when used as a component circuit of a digital phase comparator. This proposed a flip-flop circuit.

The present invention will be described in detail below based on drawings showing embodiments thereof.

In Figure 1, 1 is a P-type MOS FET11.12
The switch circuit is composed of N-type MOS FETs 13 and 14, and the FET 14 has a small gain factor.

2 is a capacitor whose charging and discharging is controlled by the switch circuit 1, and 3 is a flip-flop, both of which are CM
It consists of an AND gate 30 and NOR gates 31 and 32 of the OS.

The first to third FETs 11, 12, and 13 are connected in series in this order between the fixed power source and the substrate potential.
A fourth FET 14 and a capacitor 2 are connected in parallel with the FET 13 between the connection point and the substrate potential.

The junction gate of FBTll, 12 is connected to the fixed power supply and also FET 13.

The junction gate of 14 is at the substrate potential.

S and R are input terminals for a set signal and a reset signal, respectively, the set signal input terminal S is connected to the insulated gate of the FET 11゜14 and one input terminal of the AND gate 30, and the reset signal input terminal R is FET12,
13 and one input terminal of the NOR gate 32.

The fixed power supply side (FET 12 side) electrode of the capacitor 2 is connected to the other input terminal of the AND gate 30.

The flip-flop 3 includes NOR gates 31 and 32 connected to form an R-S flip-flop, and an A gate whose output terminal is connected to one input terminal of the NOR gate 31.
By connecting the ND gate 30 as described above, the set signal and reset signal to be applied to the set signal input terminal S and reset signal input terminal R, respectively, and the signal appearing on the fixed power supply side electrode of the capacitor 2 are connected. The potential is used as three inputs, and NOR gates 31 and 32
The respective output terminals are complementary output terminals Q and Q, respectively.

The operation of the circuit of the present invention configured as shown on paper will be explained based on FIG.

First, it is assumed that neither the set signal nor the reset signal appears (terminals S and R are at "L" level).

In this state, FETs 11 and 12 are turned on and FETs 13 and 1 are turned on.
Since capacitor 4 is off, capacitor 2 is charged.
The potential ■ is at the “H1 level.

On the other hand, since the terminal S is at the "Lt+ level", the output of the AND gate 30 is "L9 level", and since the terminal 7R connected to the one input terminal of the NOR gate 32 is also at the "Ln level", the output terminals Q and q can take the "L17" and "Hjl" level states, ie, the reset state, respectively.

When the set signal is input and the terminal S becomes "H1 level" (■), FgTll turns off and 14 turns on, and the terminal S side input of the AND gate 30 becomes "'H".
'' level, and the output changes to the ``H'' level, so that at the time of rising, the terminals Q and Q are at the high level H'' and 1, respectively.
(It becomes Ll+ level and changes to set state.

Contrary to the above, if terminals Q and Q are at the "Ht+" and "L" levels, respectively, and are in the set state before the set signal is input, the state will not change even when the set signal is input. In short, in any case, this circuit is set by inputting the set signal.

- When the FET 14 is turned on, the charge stored in the capacitor 2 is discharged through the FET 14, so the potential ■ gradually decreases with a time constant determined by the ON resistance of the FET 14, and the potential V, that is, the AND gate 30 His single-handed ability will turn to "L" level.

Next, when the reset signal is input while the set signal is being input and the terminal R becomes ") (9 levels) (■),
Since the power of the NOR gate 32 becomes "H" level, the decreasing potential V causes the AND gate 30 to reach "H" level.
Regardless of whether it is recognized as the 'L' level, the output terminals Q and Q are inverted and enter the reset state.

In other words, reset is given priority.

In addition, by inputting the reset signal, FET 12 is turned off and FET 13 is turned on, and if there is any charge remaining in capacitor 2, the discharge is also carried out through FET 13, and the potential ■ is recognized as "L 1 level". level rapidly decreases.

However, while the set signal is being input, the reset signal disappears and the terminals S and R become "H" and "
When it reaches the L l+ level (■), the R input terminals of the NOR gate 32 become the "L n level," but since the FET 11 is off, the capacitor 2 is not charged and the potential ■ becomes j
(Since L remains at 1 level, output terminals Q and Q remain at 4 L I+.

“H9 level will be maintained and the reset state will continue.

In other words, the set signal is effective for setting this flip-flop circuit only at its rising edge.

When the set signal disappears while the reset state continues (■), the switch circuit 1 returns to its initial state, and charging of the capacitor 2 starts, and the potential ■ becomes the "H97 level." AND gate 30 S
Since the side input is at the "L1" level, the output of the AND gate 30 remains at the "L" level, and the reset state continues as it is.

Next, consider the case (2) in which the reset signal is first input in this reset state.

In this case, the FET 13 is turned on, the charge in the capacitor 2 is immediately discharged through the FET 13, and the potential (2) quickly decreases.

As a result, the input on the capacitor 2 side of the AND gate 30 becomes "L'" level, but the output of the AND gate 30 becomes "L'" level.
L remains at n level and does not change.

Therefore, the reset state continues as it is.

If the set signal is input while the reset signal is being input (■), the terminal S side input of the AND gate 30 becomes the "Hn level, but as described above, the capacitor 2
Since the side input, that is, the potential ■ remains at the "Ln level," the reset state continues.

As described above, even if the reset signal disappears (■) while the set signal is being manually input, the reset state continues.

In this way, the flip-flop circuit of the present invention charges the capacitor 2 via the FETs 11 and 12 when neither the set signal nor the reset signal is input, and charges the capacitor 2 via the FET 13 when the reset signal is input. Then, when the set signal is input again, the fourth FET
The switch circuit 1 is configured to discharge the capacitor 2 through the capacitor 14, and the set signal, the reset signal, and the potential of the capacitor 2 are used as input signals, and when the set signal is input when the capacitor 2 is charged. and a flip-flop 3 that is reset when a reset signal is input, and is reset when a reset signal is input when the capacitor 2 is not charged, and is set at the rising edge of the set signal. and is configured to be reset preferentially by a reset signal.

Note that it may be configured to be set at the falling edge of the set signal.

The flip-flop circuit of the present invention, which is configured and operates as shown in FIG. 3, uses two circuits A and B and one NOR gate C, as shown in FIG. It is used when constructing a digital phase comparator such as the one disclosed in Japanese Patent Application No. 52-57188.

That is, the comparison signal Vf is input to the set terminal S of one flip-flop circuit A, the reference signal ■ is input to the set terminal S of the other flip-flop circuit B, and the output of the terminal Q of both circuits A and B is input. are the two inputs of NOR gate C, and the output of NOR gate C is input to the reset terminal R of both circuits A and H, and both circuits A and B
The output of each terminal Q is taken out as a pulse signal corresponding to the phase difference between the output signal of the phase comparator, that is, the reference signal 8 and the comparison signal Vf.

Since such a phase comparator can be constructed by making all the circuit parts of the present invention into CMOS as shown in FIG. 4, it can be operated with low power and low voltage, and the power consumption can be reduced. Of course, there are advantages in that malfunctions caused by electrostatic coupling and electromagnetic coupling can be reduced and reliability can be improved.

[Brief explanation of drawings]

The drawings show embodiments of the present invention; FIG. 1 is a schematic circuit diagram of a flip-flop circuit according to the present invention, FIG. 2 is a time chart for explaining its operation, and FIG. FIG. 4 is a schematic circuit diagram of a digital phase comparator configured using a circuit, and FIG. 4 is a circuit diagram of the circuit of the present invention, which is entirely CMOS. 1...Switch circuit, 2...Capacitor, Total...Flip-flop, 11, 12, 13
, 14...FET, 30...AND gate, 31, 32...NOR gate.

Claims (1)

[Claims] 1 Charges the capacitor through the first and second FETs when both the set signal and the reset signal are not input, and charges the capacitor through the third FET when the reset signal is input. A switch circuit configured to discharge the capacitor via a fourth FET when a set signal is input; a flip-flop that is set when a set signal is input, reset when a reset signal is input, and further reset when a reset signal is input when the capacitor is not charged; 1. A flip-flop circuit configured to be set when a set signal rises or falls, and to be preferentially reset by a reset signal.