JPS5949697B2 - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS5949697B2 JPS5949697B2 JP54159954A JP15995479A JPS5949697B2 JP S5949697 B2 JPS5949697 B2 JP S5949697B2 JP 54159954 A JP54159954 A JP 54159954A JP 15995479 A JP15995479 A JP 15995479A JP S5949697 B2 JPS5949697 B2 JP S5949697B2
- Authority
- JP
- Japan
- Prior art keywords
- space
- sealing material
- semiconductor element
- hermetically sealed
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
- H10W76/10—Containers or parts thereof
- H10W76/12—Containers or parts thereof characterised by their shape
- H10W76/15—Containers comprising an insulating or insulated base
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Casings For Electric Apparatus (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置、特にパッケージ型半導体装置に関
するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, particularly a packaged semiconductor device.
従来この種の半導体装置を第1図に示して説明する。A conventional semiconductor device of this type will be described with reference to FIG.
すなわち、パッケージ基体1はセラミックなどの一体物
からなつており、このパッケージ基体1上には半導体素
子2が装着されると共に、この半導体素子2を大気から
保護するために、その周囲に素子空間4を残して蓋3に
より包持させ、この蓋3をシール材5によりシールして
、素子空間4を気密封止するようにしている。この場合
、前記シール材5としては半田などの金属、ガラス、セ
ラミック等の無機材料、樹脂等の有機材料があてられ、
各々に要求される品質やコストなどにより選択して使用
されている。し力化、上記構造の半導体装置において、
シール材が金属材料によるときは比較的気密度を高く保
持できるものの、メタライズの必要性があり、かつ封止
に特別の高温炉を必要とするばかりか、材料自体も高価
でしかも徐々に外気中の水分が拡散浸透して素子特性の
劣化を招く虞れがあつた。また、無機および有機材料は
安価でかつ容易に封止でき、特に樹脂シールには加熱も
不要にできる利点があるが、一般に気密度が悪くて高信
頼度のものには適用できないなどの不都合があつた。本
発明は従来のこのような実情に鑑み、半導体素子を内外
2重の密閉空間により保護させるとともに、内、外の圧
力差を零あるいは陽圧にすることにより、信頼性の向上
をはかり、しかも容易にかつ安価な半導体装置を提供す
ることを目的とするものである。That is, the package base 1 is made of a single piece such as ceramic, and a semiconductor element 2 is mounted on the package base 1. In order to protect the semiconductor element 2 from the atmosphere, an element space 4 is provided around it. The element space 4 is hermetically sealed by sealing the lid 3 with a sealing material 5. In this case, the sealing material 5 is made of metal such as solder, inorganic material such as glass or ceramic, or organic material such as resin.
They are selected and used depending on the quality and cost required for each. In the semiconductor device with the above structure,
When the sealing material is made of metal, it is possible to maintain a relatively high airtightness, but not only does it require metallization and a special high-temperature furnace for sealing, but the material itself is expensive and gradually leaks into the outside air. There was a risk that the moisture would diffuse and penetrate, leading to deterioration of device characteristics. In addition, inorganic and organic materials are inexpensive and can be easily sealed, and resin seals in particular have the advantage of not requiring heating, but they generally have disadvantages such as poor airtightness and cannot be applied to highly reliable products. It was hot. In view of these conventional circumstances, the present invention aims to improve reliability by protecting a semiconductor element with a double sealed space inside and outside, and by reducing the pressure difference between the inside and outside to zero or positive pressure. The purpose is to provide a semiconductor device that is easy and inexpensive.
以下本発明にかかる装置の実施例につき、第2図を参照
して詳細に説明する。Hereinafter, embodiments of the apparatus according to the present invention will be described in detail with reference to FIG.
第2図は本発明の一実施例を示す断面図であり、同図に
おいて第1図と同一部分は同一符号を用いてある。FIG. 2 is a sectional view showing one embodiment of the present invention, and in this figure, the same parts as in FIG. 1 are designated by the same reference numerals.
この実施例では、パッケージ基体1上に上記従来例と同
様にして半導体素子2を装着した後、この半導体素子2
を包持するように内部に素子空間4を残して内蓋6を施
し、この内蓋6を内部シール材□によりパッケージ基体
1に固着させる。そして、前記内蓋6を包持するように
これらの間に絶縁空間10を残して外蓋8を施し、この
外蓋8を外部シール材9により同様にパッケージ基体1
に固着させることにより、前記半導体素子2を第1の素
子空間4と第2の絶縁空間10とによつて大気から2重
に気密封止する構造としたものである。この場合、前記
内部シール材7と外部シール材9はそれぞれ異なつた凝
固温度をもつ材料からなる。ここで、前記内蓋6を封止
する温度より外蓋8を封止する温度を少し高くすること
により、素子空間4より絶縁空間10に残留封止される
ガスの圧力を低くすることができ、素子空間4への圧力
差によるガス浸入を防止している。In this embodiment, after a semiconductor element 2 is mounted on a package base 1 in the same manner as in the conventional example, this semiconductor element 2 is
An inner cover 6 is applied leaving an element space 4 inside so as to enclose the elements, and the inner cover 6 is fixed to the package base 1 with an inner sealing material □. Then, an outer cover 8 is applied leaving an insulating space 10 between them so as to enclose the inner cover 6, and the outer cover 8 is attached to the package base 1 using an external sealing material 9.
By fixing the semiconductor element 2 to the air, the semiconductor element 2 is doubly hermetically sealed from the atmosphere by the first element space 4 and the second insulating space 10. In this case, the internal sealing material 7 and the external sealing material 9 are made of materials having different solidification temperatures. Here, by setting the temperature at which the outer cover 8 is sealed a little higher than the temperature at which the inner cover 6 is sealed, the pressure of the gas remaining sealed in the insulating space 10 can be lowered than in the element space 4. , gas intrusion into the element space 4 due to pressure difference is prevented.
また、内部シール材7と外部シール材9に同一凝固温度
を有する材料を用いた場合においても素子空間4と絶縁
空間10の間の圧力差はなくすことができる。Further, even when materials having the same solidification temperature are used for the internal sealing material 7 and the external sealing material 9, the pressure difference between the element space 4 and the insulating space 10 can be eliminated.
したがつて、上記実施例の半導体装置では、半導体素子
2を内蓋6と外蓋8とによる第1の素子空間4および第
2の絶縁空間10の2重空間によつて気密封止され、そ
のうえ素子空間4は絶縁空間10より陽圧あるいは等圧
に保持されているから、素子空間4への大気中の水蒸気
等の不純ガスの浸入速度を著るしく低減できるので、内
部および外部の各シール材7,9に樹脂材料を用いても
、半導体素子2を充分に保護することができる。Therefore, in the semiconductor device of the above embodiment, the semiconductor element 2 is hermetically sealed by the double space of the first element space 4 and the second insulating space 10 formed by the inner cover 6 and the outer cover 8, Furthermore, since the element space 4 is maintained at a more positive or equal pressure than the insulating space 10, the rate of infiltration of impurity gases such as water vapor from the atmosphere into the element space 4 can be significantly reduced. Even if a resin material is used for the sealants 7 and 9, the semiconductor element 2 can be sufficiently protected.
以上詳述したように本発明によれば、極めて簡単な構成
によつて半導体素子を大気から保護することができると
ともに、高信頼性でしかも容易にかつ安価な半導体装置
を提供することができるという効果がある。As detailed above, according to the present invention, a semiconductor element can be protected from the atmosphere with an extremely simple configuration, and a highly reliable, easy and inexpensive semiconductor device can be provided. effective.
第1図は従来のパツケージ型半導体装置の一例を示す断
面図、第2図は本発明にかかる半導体装置の一実施例を
示す断面図である。
1・・・・・・パツケージ基体、2・・・・・・半導体
素子、4・・・・・・素子空間、6・・・・・・内蓋、
7・・・・・・内部シール材、8・・・・・・外蓋、9
・・・・・・外部シール材、10・・・・・・絶縁空間
。FIG. 1 is a sectional view showing an example of a conventional package type semiconductor device, and FIG. 2 is a sectional view showing an embodiment of the semiconductor device according to the present invention. DESCRIPTION OF SYMBOLS 1...Package base, 2...Semiconductor element, 4...Element space, 6...Inner lid,
7... Internal sealing material, 8... Outer lid, 9
...External sealing material, 10...Insulating space.
Claims (1)
体素子を包囲するように内蓋を施して気密封止された第
1の素子空間と、前記内蓋を包囲するように外蓋を施し
て気密封止された第2の絶縁空間とにより前記半導体素
子を2重に気密封止する構造とし、前記内蓋を気密封止
する内部シール材の凝固温度を、前記外蓋を気密封止す
る外部シール材の凝固温度よりも低くもしくは同じに選
択したことを特徴とする半導体装置。1. On a package base in which a semiconductor element is provided, a first element space is formed, which is hermetically sealed by applying an inner lid so as to surround the semiconductor element, and a first element space is hermetically sealed by applying an outer lid to surround the inner lid. The semiconductor element is doubly hermetically sealed by a second hermetically sealed insulating space, and the solidification temperature of the internal sealing material that hermetically seals the inner lid is controlled by the solidifying temperature of the internal sealing material that hermetically seals the outer lid. A semiconductor device characterized by having a solidification temperature lower than or equal to the solidification temperature of a sealing material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54159954A JPS5949697B2 (en) | 1979-12-10 | 1979-12-10 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54159954A JPS5949697B2 (en) | 1979-12-10 | 1979-12-10 | semiconductor equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5683048A JPS5683048A (en) | 1981-07-07 |
| JPS5949697B2 true JPS5949697B2 (en) | 1984-12-04 |
Family
ID=15704788
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP54159954A Expired JPS5949697B2 (en) | 1979-12-10 | 1979-12-10 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5949697B2 (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57197471A (en) * | 1981-05-29 | 1982-12-03 | Sekisui Chem Co Ltd | Blood coagulation accelerant |
| JP2907914B2 (en) * | 1989-01-16 | 1999-06-21 | シーメンス、アクチエンゲゼルシヤフト | Sealing method and package for electric or electronic device or module |
| US6643919B1 (en) * | 2000-05-19 | 2003-11-11 | Siliconware Precision Industries Co., Ltd. | Method of fabricating a semiconductor device package having a core-hollowed portion without causing resin flash on lead frame |
| CN105144371A (en) * | 2013-04-29 | 2015-12-09 | Abb技术有限公司 | Module arrangement for power semiconductor devices |
| JP2015220330A (en) * | 2014-05-16 | 2015-12-07 | 日本電気硝子株式会社 | Light emitting device and manufacturing method thereof |
| WO2017110727A1 (en) * | 2015-12-25 | 2017-06-29 | 株式会社村田製作所 | Piezo-oscillator and piezoelectric oscillation device |
| WO2018092572A1 (en) * | 2016-11-16 | 2018-05-24 | 株式会社大真空 | Quartz oscillation device |
| JP7482399B2 (en) * | 2021-08-12 | 2024-05-14 | 株式会社村田製作所 | Piezoelectric vibrator, piezoelectric oscillator, and method for manufacturing piezoelectric vibrator |
| JP7510610B2 (en) * | 2021-08-12 | 2024-07-04 | 株式会社村田製作所 | Piezoelectric vibrator, piezoelectric oscillator, and method for manufacturing piezoelectric vibrator |
| JP7511816B2 (en) * | 2021-08-12 | 2024-07-08 | 株式会社村田製作所 | Piezoelectric vibrator, piezoelectric oscillator, and method for manufacturing piezoelectric vibrator |
-
1979
- 1979-12-10 JP JP54159954A patent/JPS5949697B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5683048A (en) | 1981-07-07 |
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