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JPS5950214B2 - Manufacturing method of semiconductor device - Google Patents
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JPS5950214B2 - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device

Info

Publication number
JPS5950214B2
JPS5950214B2 JP54060182A JP6018279A JPS5950214B2 JP S5950214 B2 JPS5950214 B2 JP S5950214B2 JP 54060182 A JP54060182 A JP 54060182A JP 6018279 A JP6018279 A JP 6018279A JP S5950214 B2 JPS5950214 B2 JP S5950214B2
Authority
JP
Japan
Prior art keywords
film
metal
alloy
semiconductor
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54060182A
Other languages
Japanese (ja)
Other versions
JPS55151334A (en
Inventor
正紀 福本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP54060182A priority Critical patent/JPS5950214B2/en
Publication of JPS55151334A publication Critical patent/JPS55151334A/en
Publication of JPS5950214B2 publication Critical patent/JPS5950214B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)

Description

【発明の詳細な説明】 本発明は半導体装置の製造方法とくに配線及び電極の製
造方法に関するものであり、半導体基板上に形成された
絶縁膜と配線、電極用金属膜との密着性を増し、さらに
コンタクト部において電極金属膜と基板を構成する半導
体との合金層を容易に形成でき、1000℃に近い高温
までの熱処理後も、浅い接合に対して電極金属のツキヌ
ケがなくする良好なオーミック性を示すコンタクトを得
ることを目的とする。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, particularly a method of manufacturing wiring and electrodes, and improves the adhesion between an insulating film formed on a semiconductor substrate and a metal film for wiring and electrodes. Furthermore, an alloy layer of the electrode metal film and the semiconductor constituting the substrate can be easily formed in the contact area, and even after heat treatment at high temperatures close to 1000 degrees Celsius, it has good ohmic properties that prevent the electrode metal from coming off in shallow junctions. The aim is to get contacts who show

ICやLSIにおいて配線面積、素子寸法の縮小及び動
作の高速化を実現するために必要な方法として次の様な
ことが考えられている。
The following methods are considered necessary to reduce the wiring area and element dimensions and increase the speed of operation in ICs and LSIs.

(1)多層アルミニウム配線にする。(1) Use multilayer aluminum wiring.

(2)ゲート電極をMo等の高融点材料にして用い、ゲ
ート電極を延長して配線とし、Si基板へ直接コンタク
トを形成する。
(2) A high melting point material such as Mo is used for the gate electrode, the gate electrode is extended to form a wiring, and a direct contact is formed to the Si substrate.

(3)半導体基板に設けられた拡散層の接合深さを浅く
0.1〜0.8μm程度にする。
(3) The junction depth of the diffusion layer provided on the semiconductor substrate is made shallow, about 0.1 to 0.8 μm.

(1)ではオーミックコンタクトを形成するため、50
0℃前後の熱処理(ジッター)が複数回行なわれ、(2
)では電極、配線形成後1000℃に近い熱処理゜が施
される。
In (1), in order to form an ohmic contact, 50
Heat treatment (jitter) at around 0℃ is performed multiple times, (2
), heat treatment at close to 1000°C is performed after electrodes and wiring are formed.

この様な長時間あるいは高温の熱処理工程を経ても(3
)に示した浅い接合に対し、電極金属は接合へのツキヌ
ケがな<、コンタクト抵抗の低い良好なオーミック性を
維持することが望ましい。上記の様な要求に対して以下
に例示する様な様々な方法が考えられて来た。
Even after such a long or high temperature heat treatment process (3
), it is desirable that the electrode metal maintain good ohmic properties with low contact resistance and no penetration into the junction. Various methods have been considered to meet the above requirements, as exemplified below.

従来のAl電極のジッターにおいてAlが接合を破壊す
るのは、ジッター時の高温でAl膜中に半導体基板を構
成する原子(シリコン)が溶解し、逆にAl原子が基板
につくられた拡散層の接合位置まで侵入するためであり
、この現象を防ぐためA1一数%Si合金膜が使用され
ている。
In the jitter of conventional Al electrodes, Al destroys the junction because the atoms (silicon) that make up the semiconductor substrate dissolve in the Al film at high temperatures during jitter, and conversely, Al atoms form a diffusion layer in the substrate. In order to prevent this phenomenon, an A1 1-1% Si alloy film is used.

Al膜中にSiを多量に含有させることにより、接合破
壊はなくせるのであるが、実用的な立場から見て、熱処
理によるSi析出、エレクトロマイグレーシヨンに対す
る信頼性の悪化、コンタクト抵抗の増大等新たな問題が
発生する。従つて現実のSi濃度は約0.5%〜1%程
度におさえる必要があるため、極めて浅い接合に対して
なお接合リークの可能性が残されている。極めて浅い接
合にも形成でき得る電極として、A1膜と半導体基板(
Si)との間に、多結晶Si膜を介在させた電極構造(
A1一多結晶Si−Si)がある。
By including a large amount of Si in the Al film, junction breakdown can be eliminated, but from a practical standpoint, there are new problems such as Si precipitation due to heat treatment, deterioration of reliability against electromigration, and increase in contact resistance. problems occur. Therefore, since the actual Si concentration needs to be suppressed to about 0.5% to 1%, there is still a possibility of junction leakage for extremely shallow junctions. The A1 film and the semiconductor substrate (
An electrode structure (Si) with a polycrystalline Si film interposed between
There is A1 (polycrystalline Si-Si).

この電極においては、熱処理によつてAlと多結晶Si
層とが優先的に反応するため、基板Siはあまり影響を
受けず、接合の破壊をほとんど起こさないようにするこ
とができる。しかしこの電極のコンタクト抵抗を下げる
には、多結晶Si層に拡散層と同一導電型となるような
不純物を高濃度に拡散するか、あるいは不純物を導入し
ない場合には多結晶Si層の厚さを300Å以下とする
必要がある。すなわち、A1と基板Siが直接接触しな
いため、コンタクト窓寸法が微小な場合、コンタクト抵
抗を十分下げることが困難であるという欠点がある。浅
い接合へ形成でき、コンタクト抵抗の低い電極としてT
i又はPtを用いる方法がある。
In this electrode, Al and polycrystalline Si are separated by heat treatment.
Since the Si layer reacts preferentially with the Si substrate, the Si substrate is not affected much, and the bond can be almost prevented from being destroyed. However, in order to lower the contact resistance of this electrode, it is necessary to diffuse into the polycrystalline Si layer a high concentration of impurity that has the same conductivity type as the diffusion layer, or, if no impurity is introduced, to reduce the thickness of the polycrystalline Si layer. must be 300 Å or less. That is, since A1 and the substrate Si do not come into direct contact with each other, there is a drawback that it is difficult to sufficiently lower the contact resistance when the contact window size is minute. T can be used as an electrode with low contact resistance and can form shallow junctions.
There is a method using i or Pt.

この方.法において、オーミツクコンタクトとするため
、Ti又はPtを基板Siのコンタクト部に被着した後
、熱処理を加えると、反応により被着金属−Si界面を
含む薄い層が一様にTiSi2、PtSiとなる。この
金属シリサイド層の厚さは、熱処理の温度、3時間によ
り制御できるので、浅い接合領域へも比較的容易に電極
形成ができる特徴をもつている。しかし、Ti.Ptは
材料が高価であり、SiO2等の絶縁物との密着性はA
lと比較して乏しいため、電極部のみに金属又は金属シ
リサイドを残して用くいなければならず、配線材料に使
用するのが難しいことが難点である。また、次の様な別
の電極形成法も提案されている。
This person. In order to make an ohmic contact, when heat treatment is applied after Ti or Pt is deposited on the contact part of the Si substrate, the thin layer including the deposited metal-Si interface uniformly forms TiSi2 and PtSi due to a reaction. Become. Since the thickness of this metal silicide layer can be controlled by the heat treatment temperature and 3 hours, it has the feature that electrodes can be formed relatively easily even in shallow junction regions. However, Ti. Pt is an expensive material, and its adhesion to insulators such as SiO2 is A
Since the metal or metal silicide must be left only in the electrode portion, it is difficult to use it as a wiring material. In addition, other electrode forming methods have been proposed as follows.

すなわち、500〜600人程度の薄いAl又はSb層
を半導体基板と接触するように設け、それら金属層表面
に不活性ガス原子を注入し、ノツクオン効果によつて金
属層を構成するAl又はSbを基板表面に導入し、コン
タクトを形成するものである。この様にすると、基板が
Siである場合、導入されたA1は、アクセプタとなり
基板表面にP型層を、SbはドナーとなりN型層を0.
1μm以下の浅い接合深さで形成すると同時にオーミツ
クコンタクトが得られる。この方法を用いてバイポーラ
゛半導体装置のエミツタ、コレタタ、ベース、CMOS
半導体装置のPチヤンネル・Nチヤンネルトランジスタ
のソース・ドレインに対する電極を同時につくるとき、
N型層、P型層となるべきコンタクト部に別々の金属を
被着せねばならず、工程が複雑となる。また、金属膜が
数百人と薄いので、実際の半導体装置へ応用するために
は、薄い金属層上にさらに最終電極・配線となるA1を
約1μm蒸着するのが普通であるが、厚いA1蒸着時の
放射線損傷の回復、薄い金属層とA1とのコンタクト抵
抗を下げるための追加熱処理が必要であり、一度浅い接
合に対する電極を形成してもこの熱処理によつて厚いA
l膜の浅い接合へのツキヌケが新たに問題となることは
Al.Sbの様な低融点金属がAlの拡散バリヤーにな
らないからである。またMOS型半導体装置のゲート配
線として有用である高融点遷移金属MO、Wや高融点遷
移金属シリサイドMOSi2、WSi2等は、材料は安
価でありゲート電極を延長してそのまま配線材としても
使用でき1000℃に近い高温熱処理が可能であるとい
う利点を有するが、やはり絶縁膜との密着性は強固でな
く、単にCVD法やスパツタ一法等で電極を形成した後
熱処理を行なつても通常基板Siに設けられた高濃度の
拡散層とほとんど反応せず、熱処理温度の上昇にともな
つてコンタクト抵抗が急激に高くなるという問題点があ
る。本発明は上記従来の例に見られる様な浅い接合に対
する電極の欠点を除去し、低いコンタクト抵抗をもち、
1000℃近くの温度まで熱処理しても浅い接合におけ
るリーダの少ない新しい電極配線の形成方法を提供する
ものである。以下本発明の製造方法を図面とともに説明
する。第1図〜第6図は半導体装置のコンタクト部近傍
の形成工程を示す断面図であり、第1図の工程は単結シ
リコン基板1に基板1と反対導電型を有する浅い拡散層
2を形成した後、SiO。
That is, a thin Al or Sb layer of about 500 to 600 layers is provided in contact with a semiconductor substrate, inert gas atoms are injected into the surface of the metal layer, and the Al or Sb constituting the metal layer is removed by the knock-on effect. It is introduced onto the surface of the substrate to form a contact. In this way, when the substrate is Si, the introduced A1 becomes an acceptor and forms a P-type layer on the substrate surface, and Sb becomes a donor and forms an N-type layer on the surface of the substrate.
An ohmic contact can be obtained at the same time by forming a shallow junction depth of 1 μm or less. Using this method, the emitter, collector, base, and CMOS of bipolar semiconductor devices can be
When simultaneously creating electrodes for the source and drain of P-channel and N-channel transistors in a semiconductor device,
Different metals must be deposited on the contact portions that are to become the N-type layer and the P-type layer, which complicates the process. In addition, since the metal film is several hundred thin, in order to apply it to an actual semiconductor device, it is normal to further evaporate about 1 μm of A1, which will become the final electrode/wiring, on the thin metal layer. Additional heat treatment is required to recover from radiation damage during evaporation and to lower the contact resistance between the thin metal layer and A1.
A new problem with Al.L film sticking to shallow junctions is that Al. This is because a low melting point metal such as Sb does not act as a diffusion barrier for Al. Furthermore, high melting point transition metals MO, W and high melting point transition metal silicides MOSi2, WSi2, etc., which are useful as gate wiring of MOS type semiconductor devices, are inexpensive materials and can be used as wiring materials by extending the gate electrode. Although it has the advantage of being able to be heat-treated at a high temperature close to °C, the adhesion with the insulating film is still not strong, and even if the electrode is simply formed by CVD or sputtering and then heat-treated, it will not work on the Si substrate. There is a problem in that the contact resistance hardly reacts with the highly concentrated diffusion layer provided in the substrate, and as the heat treatment temperature increases, the contact resistance increases rapidly. The present invention eliminates the drawbacks of electrodes for shallow junctions as seen in the above conventional examples, has low contact resistance,
The present invention provides a new method for forming electrode wiring that has fewer leaders in shallow junctions even when heat-treated to temperatures close to 1000°C. The manufacturing method of the present invention will be explained below with reference to the drawings. 1 to 6 are cross-sectional views showing the formation process near the contact portion of a semiconductor device. The process in FIG. 1 forms a shallow diffusion layer 2 having a conductivity type opposite to that of the substrate 1 on a single silicon substrate 1. After that, SiO.

膜3を1,2の表面上に形成し、拡散層2の上にある膜
3の一部をフオトエツチングにより選択的に開口してコ
ンタクト窓を設けた段階を示している。次に第1図の工
程で形成された表面全面にわたり、高融点遷移金属であ
るMO膜4を約500入の厚さとなるよう、スパツタリ
ング、電子ビーム蒸着等で被着する(第2図)。さらに
MO膜4を通して、Arのような不活性ガスイオン又は
拡散層2と同一導電型となるような不純物イオンすなわ
ち基板と反対導電型不純物をイオン注入法により、MO
膜4より下層特に膜4と拡散層2の界面を含む領域に導
入する。このとき、MO膜4の表面より入射したイオン
はMO原子と衝突し、そのエネルギーを受け取つたMO
原子はノツクオン効果により拡散層2中に格子欠陥を生
成しながら進み拡散層2の極く表面近傍で停止して拡散
層2中に導入されるので、MO4と拡散層2との界面附
近に多数の格子欠陥を含むMO−Si合金層5が形成さ
れることになる。
A stage is shown in which a film 3 is formed on the surfaces of layers 1 and 2, and a part of the film 3 above the diffusion layer 2 is selectively opened by photoetching to provide a contact window. Next, an MO film 4 made of a high melting point transition metal is deposited over the entire surface formed in the step of FIG. 1 to a thickness of approximately 500 mm by sputtering, electron beam evaporation, etc. (FIG. 2). Furthermore, through the MO film 4, inert gas ions such as Ar or impurity ions having the same conductivity type as the diffusion layer 2, that is, impurities of the opposite conductivity type to the substrate, are implanted into the MO film 4.
It is introduced into a layer below the film 4, particularly in a region including the interface between the film 4 and the diffusion layer 2. At this time, the ions incident from the surface of the MO film 4 collide with MO atoms, and the MO atoms receive the energy.
Atoms proceed while generating lattice defects in the diffusion layer 2 due to the knock-on effect, stop very close to the surface of the diffusion layer 2, and are introduced into the diffusion layer 2, so that a large number of atoms are generated near the interface between MO4 and the diffusion layer 2. A MO-Si alloy layer 5 containing lattice defects is formed.

具体的な条件はMO4の膜厚が500Λ、注入イオンが
Arの場合、注入エネルギーを約100KeV、DOs
e量1015〜 5×1015/Cm2とすれば、Ar
の濃度ピークはMO4と拡散層2の界面近傍に位置し、
MO−Si合金層5の厚さは約300Λにすることがで
きる。
The specific conditions are: MO4 film thickness is 500Λ, implanted ions are Ar, implantation energy is approximately 100 KeV, DOs
If the amount of e is 1015~5×1015/Cm2, Ar
The concentration peak of is located near the interface between MO4 and the diffusion layer 2,
The thickness of the MO-Si alloy layer 5 can be approximately 300Λ.

従つて合金層5は接合深さより十分小さい深さにおさえ
ることができる。また上記MO−Siコンタクト面だけ
でなくSiO2膜3の非常に薄い表面層にもノツクオン
効果によるMO原子が導入され、MO−SiO,遷移層
が形成できるため、MO4とSiO。膜3との密着性を
強固にすることができる (第3図)。この後、さらに
MO膜6を厚さ約1ftmに被着した後(第4図)、フ
オトエツチングを行い、膜4及び6を選択的に除去して
配線パターンを形成する (第5図)。
Therefore, the depth of the alloy layer 5 can be kept sufficiently smaller than the bonding depth. Furthermore, MO atoms are introduced not only into the MO-Si contact surface but also into the very thin surface layer of the SiO2 film 3 due to the knock-on effect, forming an MO-SiO transition layer. It is possible to strengthen the adhesion with the membrane 3 (Fig. 3). Thereafter, an MO film 6 is further deposited to a thickness of about 1 ftm (FIG. 4), and then photoetching is performed to selectively remove the films 4 and 6 to form a wiring pattern (FIG. 5).

なお金属膜6はMO以外の金属、例えばALAl/Si
等であつてもよい。層5はイオン注入による欠陥を多数
含んだ一様に均質な層であり、それらをアニールすると
共に高融点金属のシリサイドとするため、400℃〜6
00℃程度の温度で熱処理をする。以上の様に本発明に
おける電極製造方法では、特にMOの様な高融点遷移金
属または半導体との合金膜を用いかつ半導体界面付近に
イオン注入を行うので、絶縁膜とMO界面に中間層をつ
くるためにMOの密着性を改善できると共に室温で一様
なMO−半導体の合金層がコンタクト界面に再現性よく
安定に形成できる。
Note that the metal film 6 is made of a metal other than MO, for example, ALAl/Si.
etc. may be used. Layer 5 is a uniformly homogeneous layer containing many defects due to ion implantation, and is heated at 400°C to 6°C in order to anneal them and turn them into silicide of high melting point metal.
Heat treatment is performed at a temperature of about 00°C. As described above, in the electrode manufacturing method of the present invention, an alloy film of a high melting point transition metal such as MO or a semiconductor is used, and ions are implanted near the semiconductor interface, so an intermediate layer is created at the interface between the insulating film and the MO. Therefore, the adhesion of MO can be improved, and a uniform MO-semiconductor alloy layer can be stably formed at the contact interface with good reproducibility at room temperature.

この合金層は、従来の方法で形成された合金層と比較し
て、高温の熱処理をしても電極を構成する金属原子と基
板半導体原子の相互拡散を阻止する効果が非常に高いこ
と、熱処理温度が上昇しても常に低いコンタクト抵抗(
10−゜Ω・ Cm2)を維持するという特別な性質を
有するものである。
Compared to alloy layers formed by conventional methods, this alloy layer is extremely effective in preventing interdiffusion between the metal atoms that make up the electrode and the semiconductor atoms of the substrate even after high-temperature heat treatment. Constantly low contact resistance (
It has a special property of maintaining a resistance of 10-゜Ω・Cm2).

従つて本発明実施例に示すような電極構造では、100
0℃近辺での熱処理を施した場合でも、イオン注入で形
成された合金層のため、相互拡散によるMOの接合への
ツキヌケはなく、浅い接合に対して耐えることができる
のである。このような性質は他の低融点金属(ALSb
等)を用いた場合には期待できないものである。
Therefore, in the electrode structure shown in the embodiment of the present invention, 100
Even when heat treatment is performed at around 0° C., because the alloy layer is formed by ion implantation, the MO does not slip into the junction due to interdiffusion, and can withstand shallow junctions. Such properties are similar to other low melting point metals (ALSb
etc.), this cannot be expected.

この性質のためMOの様な高融点金属ゲート配線を有す
るMOS型(NMOS、CMOSを含む)高速LSIの
高密度化に必要で、1000℃程度の高温熱処理プロセ
スに耐える必要のあるMO−Si直接コンタクト形成に
対しても本発明はその効果を発揮するものである。本発
明の製造方法はMO以外の高融点遷移金属膜あるいはM
OSi。の様な高融点遷移金属と半導体を構成する元素
との合金膜を半導体基板とコンタクトさせる場合にも用
いることができる。特に合金膜は、半導体基板とほとん
ど同様な耐酸性を有し、金属を用いる場合と比較して半
導体プロセスにおける各種表面処理を容易にするという
利点がある。MO6をAlやAl/Siに変えてもこの
高融点金属−半導体の合金層5は、十分なAl拡散バリ
ヤーとして作用するので熱処理温度を上げることができ
る。
Because of this property, it is necessary to increase the density of MOS type (including NMOS and CMOS) high-speed LSIs that have high-melting point metal gate wiring such as MO, and MO-Si direct contact that must withstand high-temperature heat treatment processes of about 1000 degrees Celsius. The present invention also exhibits its effects in contact formation. The manufacturing method of the present invention is a high melting point transition metal film other than MO or M
OSi. It can also be used when an alloy film of a high melting point transition metal and an element constituting a semiconductor is brought into contact with a semiconductor substrate. In particular, alloy films have almost the same acid resistance as semiconductor substrates, and have the advantage of facilitating various surface treatments in semiconductor processes compared to the case of using metals. Even if MO6 is replaced with Al or Al/Si, the high melting point metal-semiconductor alloy layer 5 acts as a sufficient Al diffusion barrier, so the heat treatment temperature can be increased.

従つて、浅い接合に対しても接合リークが問題とならな
い電極形成が容易にできるのである。しかも、MO等の
高融点遷移金属はAlやSbとは異なり半導体基板中に
導入されてもドナーやアクセプタにならず、半導体基板
の導電型に何ら影響を与えないのでN型、P型半導体表
面層が共存する場合にも両層へ同時に簡単な工程で低い
コンタクト抵抗をもつ、オーミツクコンタクトが形成で
きる。このためバイポーラトランジスタやCMOSデバ
イスの浅い接合に対する電極形成法として有効である。
Therefore, even for shallow junctions, electrodes can be easily formed without junction leakage being a problem. Moreover, unlike Al and Sb, high melting point transition metals such as MO do not become donors or acceptors even when introduced into a semiconductor substrate, and do not affect the conductivity type of the semiconductor substrate. Even when layers coexist, ohmic contacts with low contact resistance can be formed simultaneously to both layers through a simple process. Therefore, it is effective as a method for forming electrodes for shallow junctions in bipolar transistors and CMOS devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図〜第5図は本発明の一実施例による半導体集積回
路装置の配線、電極の製造工程を示す断面図で゛ある。 ゛1・・・・・・シリコン基板、
2・・・・・・シリコン基板1と反対導電型を有する拡
散層、3・・・・・・SiO2膜、4・・・・・・薄い
MO膜、5・・・・・・MO−Si合金層、6・・・・
・・厚いMO膜。
1 to 5 are cross-sectional views showing the manufacturing process of wiring and electrodes of a semiconductor integrated circuit device according to an embodiment of the present invention.゛1... Silicon substrate,
2... Diffusion layer having a conductivity type opposite to that of the silicon substrate 1, 3... SiO2 film, 4... Thin MO film, 5... MO-Si Alloy layer, 6...
...Thick MO film.

Claims (1)

【特許請求の範囲】 1 半導体基板の表面に形成された絶縁膜の一部を開口
して前記半導体基板表面を露出させた後前記開口部をお
おうように高融点遷移金属の膜又はこの金属と前記半導
体を構成する元素との合金膜を被着する工程と、前記金
属膜又は合金膜上からイオン注入して、前記金属膜又は
合金膜を構成する原子を前記基板内に導入し、前記金属
又は合金膜を構成する原子と前記半導体を構成する原子
との合金層を形成する工程と、前記イオン注入後、前記
合金層を熱処理して前記半導体基板と前記金属膜又は合
金膜とのコンタクトを形成する工程と、前記金属膜又は
合金膜上にさらに金属膜を形成する工程を含むことを特
徴とする半導体装置の製造方法。 2 金属膜又は合金膜上から注入イオン濃度が前記金属
膜又は合金膜と半導体基板との界面近傍においてほぼ最
大となるようにイオン注入する工程を含むことを特徴と
する特許請求の範囲第1項に記載の半導体装置の製造方
法。 3 高融点遷移金属がMo膜よりなることを特徴とする
特許請求の範囲第1項又は第2項に記載の半導体装置の
製造方法。
[Claims] 1. After opening a part of an insulating film formed on the surface of a semiconductor substrate to expose the surface of the semiconductor substrate, a film of a high melting point transition metal or a film of this metal is formed to cover the opening. a step of depositing an alloy film with an element constituting the semiconductor; and a step of implanting ions from above the metal film or alloy film to introduce atoms constituting the metal film or alloy film into the substrate; or a step of forming an alloy layer of atoms constituting an alloy film and atoms constituting the semiconductor, and after the ion implantation, heat treating the alloy layer to establish contact between the semiconductor substrate and the metal film or the alloy film. A method for manufacturing a semiconductor device, comprising the steps of forming a metal film or an alloy film, and further forming a metal film on the metal film or alloy film. 2. Claim 1, which includes the step of implanting ions from above the metal film or alloy film so that the implanted ion concentration becomes approximately maximum in the vicinity of the interface between the metal film or alloy film and the semiconductor substrate. A method for manufacturing a semiconductor device according to . 3. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein the high melting point transition metal is a Mo film.
JP54060182A 1979-05-16 1979-05-16 Manufacturing method of semiconductor device Expired JPS5950214B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54060182A JPS5950214B2 (en) 1979-05-16 1979-05-16 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54060182A JPS5950214B2 (en) 1979-05-16 1979-05-16 Manufacturing method of semiconductor device

Publications (2)

Publication Number Publication Date
JPS55151334A JPS55151334A (en) 1980-11-25
JPS5950214B2 true JPS5950214B2 (en) 1984-12-07

Family

ID=13134753

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54060182A Expired JPS5950214B2 (en) 1979-05-16 1979-05-16 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5950214B2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5832415A (en) * 1981-08-20 1983-02-25 Sanyo Electric Co Ltd Reducing method of contact resistance
US5210042A (en) * 1983-09-26 1993-05-11 Fujitsu Limited Method of producing semiconductor device
JPS60130844A (en) * 1983-12-20 1985-07-12 Toshiba Corp Manufacture of semiconductor device
JPS61222175A (en) * 1985-03-01 1986-10-02 Fujitsu Ltd Manufacture of semiconductor memory device
US5444024A (en) * 1994-06-10 1995-08-22 Advanced Micro Devices, Inc. Method for low energy implantation of argon to control titanium silicide formation

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5137465B2 (en) * 1971-09-13 1976-10-15
JPS5141957A (en) * 1974-10-07 1976-04-08 Nippon Electric Co Handotaisochino denkyokukeiseihoho

Also Published As

Publication number Publication date
JPS55151334A (en) 1980-11-25

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