JPS5950944B2 - Digital integrated circuit function tester - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital integrated circuit functional tester particularly suitable for functional testing of integrated circuits equipped with sequential circuits.

As is well known in electronic circuits, there are combinational circuits in which one output corresponds to one input, such as AND and OR gates, and sequential circuits, in which one output is generated only when multiple people are applied, such as in shift registers and counters. ) There is a circuit.

Furthermore, as is well known, integrated circuits are equipped with a large number of electronic circuits, and it is necessary to perform various functional tests at all stages of manufacturing the integrated circuits. For testing, it is convenient to prepare a standard sample STD, apply the same input signal to the device under test DUT, compare the outputs, and judge the outputs to be good if they are the same and bad if they are different. By the way, in the case of the above-mentioned combinational circuit, the input and output are 1:1.
Since there is a correspondence, output comparisons can be performed after an appropriate time after the element state change has finished after each input is applied, but in the case of sequential circuits, there is not a one-to-one correspondence, so selecting the point of output comparison is difficult. be. Usually a clock pulse with a suitable period,
Alternatively, methods such as detecting changes in the output of a standard sample and comparing them when the changes occur are used, but if the device under test produces regular erroneous outputs, even these test methods cannot perform output inspection. Although it is possible, this method has the drawback that it cannot detect cases where a momentary erroneous output occurs and then immediately recovers. The present invention aims to improve this problem and provide a tester that can detect any erroneous output from the device under test, even if it is of such a nature.

That is, the digital integrated circuit function tester of the present invention includes a circuit that inputs the same test pattern to the device under test and the standard device;
A pair of level comparators that change high or low according to changes in the output of the device under test and the standard device, and produce outputs of the same high or low level regardless of the input level, and when the outputs of these level comparators change. , which is characterized by comprising a pair of circuits each generating a strobe pulse, and a pattern comparator that compares the outputs of the pair of level comparators when a strobe pulse is input from either one of the circuits. , which will now be described in detail with reference to the drawings.
FIG. 1 shows an embodiment of the present invention, in which 1 is a pattern generator, 2 and 3 are drivers, 4 is a standard device, 5 is a device under test, 6 and 7 are level comparators, 8 and 9 are delay circuits, 1
0 is a pattern comparator, 11 and 12 are one-shot multivibrators, and 13 is a good/bad signal generator.

The pattern generator 1 outputs a test pattern having the waveform shown, for example, in FIG. Therefore, the standard device 4 and the device under test 5 produce outputs, but since the inputs are the same, their outputs are the same if they are normal. Level comparators 6 and 7 receive the outputs of these devices 4 and 5, and change to H and L according to the H (high) and L (mouth one) levels, and maintain a constant H level even if the input level differs slightly.
, L level. This means that even if the devices 4 and 5 produce TTL level output,
Even if the pattern comparator 10 generates an output at the OS level, the pattern comparator 10 is designed to always receive a signal at the same level. The outputs of level comparators 6 and 7 are sent to pattern comparator 10 through delay circuits 8 and 9.
The signal is input to the one-shot multi 11 and 12 to generate a strobe pulse. That is, this one-shot multi generates a pulse when the level comparator changes its output, and this pulse instructs the pattern comparator 10 to compare the outputs of the level comparators 6 and 7. As mentioned above, if the outputs of the level comparators 6 and 7 are normal, they match. However, if there is an abnormality, for example, the output of the level comparator 6 and the output of the OTS1 level comparator 7 in FIG. 2 will be 20Td, resulting in a mismatch. In particular, temporary output abnormalities such as the portions P1 and P2 of the output 0Td are difficult to detect using the conventional method. In this circuit, when there is a change in the output of the comparators 6 and 7, the one-shot multis 11 and 12 generate a strobe pulse STb, so the comparator 10 compares the outputs 0Ts and 0Td and generates a fail signal FG indicating a point of disagreement.
STa in Fig. 2 is a strobe pulse of the conventional method, and in this case, the strobe pulse is generated approximately in the middle between changes in the input 1N, and such periodic tests detect abnormalities P1, P2, and P3. It is difficult to do so. Note that the delay circuits 8 and 9 are for timing purposes, and are used to compensate for delays in the one-shot multis 11 and 12 so that the outputs 0Ts and OTd at the time of change can be compared. As is clear from the above explanation, according to the present invention, each time there is a change in the output of either the standard device or the device under test, the outputs of both devices are compared to detect an abnormality, so the comparison is virtually always continuous. It means that you are doing
Even temporary erroneous outputs can be detected, making it possible to perform extremely complete tests.

This test equipment can also easily test printed circuit boards.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a waveform diagram for explaining the operation. In the drawing, 5 is a device under test, 4 is a standard device, PG is a pattern generator, 2 and 3 are drivers, 6 and 7 are level comparators, 11 and 12 are strobe pulse generators, and 10 is a pattern comparator.

Claims (1)

[Claims] 1 A circuit that inputs the same test pattern to the device under test and the standard device, and a circuit that changes high and low depending on the output changes of the device under test and the standard device, and outputs the same high and low levels regardless of the input level. a pair of level comparators that are generated, a pair of circuits that each generate a strobe pulse when the outputs of these level comparators change, and an output of the pair of level comparators that generates a strobe pulse when a strobe pulse is input from either of the circuits. A digital integrated circuit functional testing machine characterized by comprising a pattern comparator for comparing.