JPS5951020B2 - Time monitoring timer set control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a time monitoring timer set control method, particularly a central processing unit, a main memory unit, a channel unit, and a plurality of line units.
In a data transmission system having an adapter, instead of conventionally having a time monitoring timer set in hardware on each line adapter to monitor time during communication, a time monitoring timer compatible with each of the above line adapters is used. This invention relates to a time monitoring timer set control system which is provided on the channel device and sets an initial value as needed by the channel device to prevent timer setting errors.

Conventionally, when communicating with a terminal device via a communication line, time has been monitored using a timer in order to prevent the communication from falling into a state of no communication when there is no response from the terminal device.

That is, measures are taken such as retrying when the timer ends. The optimum value for setting the time length of this timer is determined using parameters such as the line speed of the communication line and the maximum length of data in one section in the communication control procedure. Therefore, there was a risk of human error in setting the time length of the timer. The present invention aims to solve the above-mentioned problems, and the time monitoring timer set control method of the present invention includes a channel device and a plurality of line adapters connected to the channel device. In a data transmission system that sends and receives data while monitoring the time between terminal devices connected to line adapters, the time monitoring timers provided for each of the line adapters are integrated on the channel device. In addition, each of the line adapters is provided with a setting section for setting information related to the speed of the corresponding line and a reading means from this setting section, and the setting section read by the reading means is provided in the channel device. Means is provided to determine the monitoring time in each of the above line adapters based on the value, and to set an initial value of each of the above timers corresponding to the monitoring time, and when communication to each of the above line adapters is started, the above time is set with the above initial value. The feature is that a monitoring timer is set.

This will be explained below with reference to the drawings. FIG. 1 shows the configuration of an embodiment of a data transmission system to which the present invention is applied, FIG. 2 shows the configuration of an embodiment of a channel device, and FIG. 3 shows the configuration of an embodiment of a line adapter. In Figure 1, CPU is a central processing unit, MEM is a main memory, C-BUS is a bus,
2 is a channel device, 2 is a microprocessor that controls the channel device, 3 is a main memory within the channel device, 4-0 to 4-7 are line adapters, and 5 is an LA bus.

Also, TIM represents evening time. central processing unit CP
When U transmits data to one terminal (not shown) connected to line adapter 4-0, for example, the process is as follows.

That is, (1) the central processing unit CPU is connected to the main memory MEM
Set the transmission data in the upper data buffer area.

Then, the channel device 1 is notified of address information representing the storage location of the transmission data and length information representing the length of the transmission data. That is, issue a send command. (
2) Thereby, the channel device 1 copies the transmission data on the main memory device MEM to the main memory 3 in the device shown in FIG. 1 under DMA control, and creates copy data. Free the data buffer area on the main memory MEM.

(3) Next, the channel device 1 issues a transmission command to the line adapter 40, and the line adapter 4-0 sends the copy data in the device's main memory 3 under DMA control.
For example, data is read one byte at a time and transmitted to a terminal device (not shown). (4) In this case, a timer is activated as necessary to monitor the time, but in the case of the present invention, a timer corresponding to each line adapter is provided on the channel device 1 as shown in FIG. , the initial value is preset when starting the timer.

(5) When all the transmissions described in the above process (3) are completed normally, the channel device] reports this to the central processing unit CPU.

(6) During the transmission described in process (3) above, if the timer TIM reaches the timer end, some kind of failure has occurred, and an interrupt is issued to the illustrated microprocessor 2. .

Data transmission is performed as conceptually explained above, but it goes without saying that when data is received from the line adapter side, the timer TIM is activated as necessary to monitor the time. stomach.

The time length of the above-mentioned timer is determined based on the line speed and the maximum length of data in one section of the communication control procedure, but in the conventional system, the timer is 4-1, . . . , by so-called hardware settings, and it can be considered that the timer is started at the time of communication. For this reason, human errors may occur when setting the time length of the timer in hardware, or flexibility may be poor when attempting to change line speeds, etc. For this reason, in the case of the present invention, timers TIM corresponding to each line adapter 4-0, 4-1, . . . are provided all at once on the channel device 1. 1 for each line adapter 4-0,
4-1, . . . , read the line speed, give the corresponding initial value to the initial value register, and preset the initial value to the counter at the start of communication.
We are trying to solve the above problems. A detailed explanation will be given below with reference to FIGS. 2 and 3.

FIG. 2 shows the configuration of an embodiment of the center side device according to the present invention.
FIG. 3 shows the configuration of an embodiment of the line adapter side according to the present invention.

In the figure, the symbols 1, 2, 3, 4-0 to 47,
5 corresponds to FIG. 1, and 8-0 to 8-7 are data buffer areas of the main memory 3 in the device, respectively, in which the above-mentioned copy data is stored. -0 to 47, 9 is the main memory address storage part in the device, and the inside is divided into 4-0 to 4-7 corresponding line adapters. Storage of DMA address information when transmitting and receiving data under DMA control, 1
0 is a length information storage section, which is internally divided into sections corresponding to each line adapter 4-0 to 4-7, and is a length that manages the number of transferred bytes when the corresponding line adapter transmits and receives data under DMA control. 11 is a DMA address information count up circuit that updates the DMA address information each time a main memory access is performed under DMA control.]
2 is a length information update circuit that updates the length information each time a data transfer is performed under DMA control; 13 is an MS/DMA encoder/decoder that manages main memory access; 14 , 15,
16 is a multiplexer, 17 is a bidirectional driver, 18-0 is a bidirectional buffer, 19-0 is a transmitting data register, and 20-0 is a transmitting data holding register, which converts it into serial data and sends it to the modem. 21-0 is a receive data holding register, which converts the received data from the modem into parallel data and transfers it, 22-0 is a receive data register, and 23-0 is a status register. Register (line interface information holding register), 24-0 is line speed setting section, 25-0,
28-0 to 28-0 are flip-flops, 29-0 is a transmission driver, 30-0 is a receiver, 31 and 32 are AND circuits, and 33 is an OR circuit.

Also, 341, 34-2, located on the left side of Figure 2,
34-3 are respective timer units TIM. 35 is an MPUiRQ encoder, and 35 is an MPUiRQ encoder, and for example, one of the above-mentioned timers has eight timers corresponding to each line adapter for each line speed.
This represents what interrupts the microprocessor 2 when an end occurs. In the case shown in the figure, the DMA address register and length information register originally located in the DMA control section provided in each line adapter 4-0, 4-1, . . . are located on the channel device 1. It is located as an internal main memory address storage section 9 and a length information storage section 10.

For example, when a DMA control request MDRQ0 is given from the line adapter 4-0, on the channel device 1, the internal main memory address storage section 9 and the length information storage section 10 correspond to the line adapter 4-0. The information is read out and stored in the main memory 3 and line adapter 4-
It can be considered that data is transmitted and received between 0 and 0.
That is, when data is transferred from the microprocessor 2 side to the line adapter 4-0 side, the microprocessor 2 transfers the line data via the driver 17 shown in FIG.
Set flip-flop 25-0 shown in adapter 4-0. This allows the flip-flop 25-
sets the transmission data start signal SDST to logic "1". At this time, the transmission data on line adapter 4-0
If the register 19-0 is empty, the flip-flop 28-0 outputs the transmit register empty status signal SBE.
Since P is set to logic "1", the AND circuit 32,
A DMA request signal MDRQ0 is issued from line adapter 4-0 via OR circuit 33. The request signal MDRQ
O is the MS/DMA encoder/decoder 1 shown in FIG.
3, and if the DMA request is permitted, the above MS/
DMA encoder/decoder 13 is connected to line adapter 4
-0, a confirmation signal MDAK0 is returned.

At this time, the main memory address storage section 9 in the device shown in FIG.
Address information is set in the length information storage section 10, and the number of bytes of data to be transferred by the DMA transfer is set as "10" in the same way in the area corresponding to the line adapter 4-0. It is set. When the confirmation signal MDAKO is returned, the DMA address A corresponding to the line adapter 4-0 is read from the internal main memory address storage section 9 and sent to the data buffer on the main memory 3 via the multiplexer 14. Area 8-
0 is accessed and the contents of the buffer area 8-0 are set in the register 19-0 shown in FIG. 3 via the driver 17. Needless to say, the data is transmitted from the adapter 4-0 to the modem at this time. Next, the DMA address A is incremented by 1 through the circuit 11 to prepare (A+1) as the next DMA address. On the other hand, length information storage section 10
The length information "10" is read out from the circuit 12, in this case it is incremented by 1 and returned to the length information storage unit 10 as information "9". Thereafter, the main memory 3 in the device is accessed one after another based on the contents of the main memory address storage section 9 in the device, and the transmission data is transferred to the line adapter 4-
It will be transferred to 0. Then, when the transmission of the 10 bytes of data described above is completed, the length information storage section 10,
Although the length information has a value of "0", a length zero signal LGZ indicating that the value has become "O" is notified to the line adapter 4-0. As a result, the AND circuit 31 shown in FIG. 3 is turned on and the flip-flop 25-0 is reset.
The DMA request signal MDRQO is not issued via the DMA request signal MDRQO. This completes the data transfer from the processor 2 side to the line adapter 4-0. On the other hand, the line
When data is transferred from the adapter 4-0 side to the miteraniro processor 2 side, when one byte of data is set in the receive data register 22-0 of the line adapter 4-0, the flip-flop 26 -0 is set and passes through the OR circuit 33 to the line adapter 4-02.
issues a DMA request signal MDRQ0.

In this case as well, DMA address information corresponding to the line adapter 4-0 is prepared in the internal main memory address storage section 9 shown in FIG.
The addresses within are fixed and prepared. - indicates the address), while the render information corresponding to the line adapter 4-0 in the length information storage section 10 has the value UO. The above DMA request signal MD
Based on RQ0, the MS/DMA encoder/decoder 133 shown in FIG. Memory 3 is accessed. The contents of the receive data register 22-0 shown in FIG.
It is then stored in the main memory 3. And in this case,
Line adapter 4- in length information storage section 10
The length information corresponding to 0 is incremented by 1 from the value "0" by the circuit 12 and returned to the length information storage section 10. When the data transfer from the line adapter 4-0 to the microprocessor 2 is completed, the line adapter 4-0 transfers the data to the microprocessor 2 using a well-known configuration not shown.
Notify by interrupting. As a result, it goes without saying that the processor 2 reads the data on the main memory 3 and transfers it to the main memory MEM shown in FIG. As explained above, data is sent and received, but
Prior to this, the channel device 1 sets the line speed setting units 24-0, 24-1, . . . to each line adapter 4-0, 4-1, . The contents of each line adapter 4-0 are read by reading the registers 23-0, 23-1, .
, 4-1, .
Prepare a timer TIM that is compatible with the adapter.

And each line adapter 4-0, 4-1,...
An initial value is determined to give the optimum timer time length for each time, and is given to the initial value register. For example, timer TI
The counter that makes up M is set to the timer by the value "127".
When a time length (counted by the number of clocks) of "80" is given to line adapter 4-0 as an end signal, the timer T corresponding to line adapter 4-0 is
The value "47" is given to the initial value register of IM. Then, when communicating with line adapter 4-0, channel device 1 activates a counter preset with the value "47" in the initial value register of timer TIM corresponding to line adapter 4-0. The same applies to each line adapter 4-1, 4-2, . . . . When the timer TIM corresponding to any line adapter reaches the timer end, the MPUiRQ
The encoder 35 is notified and an interrupt is issued to the microprocessor 2. As explained above, according to the present invention, the timers corresponding to each line adapter are integrated on the channel device 1, and
An initial value is determined and held in an initial value register, and at the start of communication, a counter preset with the contents of the initial value register is activated.

This eliminates human error when setting the timer time length, and improves flexibility when switching line speeds.

[Brief explanation of the drawing]

FIG. 1 shows the configuration of an embodiment of a data transmission system to which the present invention is applied, FIG. 2 shows the configuration of an embodiment of a channel device, and FIG.
The figure shows one embodiment of a line adapter configuration. In the figure, CPU is a central processing unit, MEM is a main memory, 1
2 is a channel device, 2 is a microprocessor, 3 is a main memory within the channel device, 4-0 to 4-7 are line adapters, TIM is a timer, 23-0 is a register, 2
4-0 represents a line speed setting section.

Claims (1)

[Claims] 1. A data transmission system that includes a channel device and a plurality of line adapters connected to the channel device, and transmits and receives data while monitoring time between the channel device and a terminal device connected to the line adapter. , a setting section for providing time monitoring timers corresponding to each of the line adapters on the channel device, and setting information related to the speed of the corresponding line to each of the line adapters; and reading means from the setting section, the channel device determines the monitoring time in each of the line adapters based on the setting value read by the reading means, and initializes each of the timers corresponding to the monitoring time. A time monitoring timer set control method, characterized in that means for setting a value is provided, and the time monitoring timer is set with the initial value at the time of starting communication to each of the line adapters.