JPH0695699B2 - Communication control device - Google Patents

Description

The present invention relates to a communication control device, and more particularly to a monitoring function for monitoring whether or not a line interface signal normally satisfies a prescribed time in a protocol.

(Prior Art) FIG. 3 is a block diagram showing a configuration of a communication control device that accommodates a plurality of lines having different communication speeds and communication protocols and has a transmission / reception clock generation unit for each line. In the figure, 21 is a communication control device, 22 is a common timer, 23 is a transmission / reception clock generation unit, 24 is a control unit, 25 is a local memory (LM), and 26 is a processor unit (PU).

In such a communication control device, when it is attempted to satisfy the time regulation etc. conventionally defined in the communication protocol, the time regulation includes a fixed time regulation unrelated to the communication speed and a time dependent on the communication speed. They can be roughly classified into regulations, and the prescribed time monitoring on the communication protocol for each line has been realized by using different means. Of these time regulations, when trying to satisfy the time regulated by the communication protocol regardless of the communication speed, for example, as shown in FIG. 4, the circuit interface in the calling sequence of the circuit switching service of the DDX network is shown. When satisfying the time stipulated for the T line, C line, and R line of the signal, that is, within 3 seconds from when the C line is turned on to when the received character SYN, SYN, + is received, compare The specified time is long. Therefore, in the conventional method, the control unit 24 shown in FIG.
A common timer 22 based on a timer value of a predetermined unit (usually a unit of 10 to 100 ms) common to all lines is provided therein, and further, a plurality of counter values according to the application for each line as shown in FIG. 5 are provided. The timer monitoring counter table 32 that can set the timer, the line timer enable table 31 that sets enable / disable of the timer (in the figure, 33 indicates the enable bit of the counter 1 from the line # 0), and the time-up not shown. A time-up queue for memorizing the occurrence of a change and waiting for processing, and a controller program for controlling these operations were provided, and the control was performed as follows. That is, each time the common timer 22 times out, a basic timer interrupt is generated, and the timer count value of the line set as valid in the line timer enable table 31 is decremented by the control of the control program. When it becomes 0, the time-up of the line is recognized, the line is queued in the time-up queue, and predetermined time-up / processing is performed in order.

However, when trying to satisfy the time regulation depending on the communication speed, for example, in the DDX network circuit switching service, as shown in FIG.
When satisfying the requirement that data can be transmitted from the time when 24 bits or more have passed, it is necessary to have a basic timer with the same communication speed in order to realize it with the above method. Is 48 kbPS, The basic timer value of is required. When such a high-speed basic timer value is used, time-up interrupts frequently occur,
The overhead on the operation of the device becomes large, and the performance of the communication control device as a whole is degraded.

Therefore, conventionally, each line interface signal line has been realized by having hardware for time monitoring. That is,
Taking the I line of the circuit switching interface as an example,
As shown in the figure, a 24-bit delay counter 71 for time monitoring dedicated to the I line, which uses the S line of the transmission / reception timing supplied from the line as a basic clock, is provided, and the I line from the line has the above-mentioned 24 bits. After inputting to the delay counter 71 and a 24-bit long time has elapsed, the I line to the inside of the apparatus is output to satisfy the time regulation as shown in FIG. In the same way as in the past, a separate hardware counter circuit was provided for monitoring the I line for a specified time, and separate line interface signal lines, such as the R line, T line, and C line, also require separate hardware. Therefore, it corresponds to the time specified for each line interface signal. Furthermore, this hardware was provided for each line.

In another example, when a modem is connected and communication is performed, the station attempting to transmit is 1 of the modem control signal.
It is necessary to control to turn on a transmission request signal (hereinafter referred to as an RS signal), which is one of the two signals, and to turn off the RS signal when the transmission is completed. In the case of half-duplex communication, in order to improve the transmission efficiency, immediately after the end of transmission, the RS signal is turned off and the transmission right of the own station is relinquished so that the other station can transmit faster. Is required.

However, for example, when communication is performed using the start-stop synchronization method as shown in FIG. 8 (a), if the RS signal is turned off immediately after sending the final transmission data (* portion), The CD off timing of the CD signal (carrier detection signal: a signal indicating that the device is detecting a carrier) when it arrives at the other modem due to propagation delay etc. is earlier than the arrival of the last bit of the transmission data. In some cases, the final transmission data becomes invalid as a result. In order to solve this problem, conventionally, as in the case of the I line, as shown in FIG. 8 (b), a specified time for each RS signal (in this case, a start bit, 8 data bits, a parity bit, It has a hardware for monitoring 1 bit of stop bit (11 bit length in total). The RS set / reset signal 83 set from inside the device is latched by the latch circuit 81, and its output is further delayed by 11 clocks. By delaying with the counter 82 and turning off the RS signal,
The means for guaranteeing the validity of the transmission data as indicated by ** in Fig. 8 (a) was taken. Also in this case, each line is realized by having the above-mentioned RS signal-specific hardware.

(Problems to be Solved by the Invention) However, in the above conventional timer control system,
In order to satisfy the time regulation that depends on the communication speed, it is necessary to install a timer monitoring circuit for each line interface signal line separately from the means for satisfying the time regulation that does not depend on the communication speed as described above. Therefore, there is a problem that the hardware increases.

The present invention solves the above-mentioned problems and implements timer monitoring for satisfying the regulation of the time depending on the communication speed, which has a conventional timer monitoring hardware for each line interface signal line of each line. Compared with, it aims at reducing the hardware and realizing an economical timer control method.

(Means for Solving Problems) The present invention provides a communication control device having a monitoring function for monitoring whether or not a line interface signal satisfies a prescribed time in a communication protocol, the line being provided for each line. A transmission / reception control unit that controls transmission / reception of each line, a transmission / reception clock generation unit that is provided for each line and supplies a transmission / reception clock to the transmission / reception control unit, and a transmission / reception clock that is provided for each line and that is output from the transmission / reception clock generation unit is a basic clock. , And any timer value can be set, and a timer circuit that outputs a time-up signal when performing time counting according to this timer value, and a timer value to be set in the timer circuit for each line, In addition, a memory for storing each line interface signal is provided, and the line interface signal is defined by the communication protocol. When it is monitored whether the time is satisfied, the timer value corresponding to the line interface signal is read from the memory and set in the timer circuit, and then it is detected whether the timer has timed out. It is configured to monitor whether the line interface signal satisfies the specified time in the communication protocol.

(Operation) For example, the operation in the case of satisfying the regulation of enabling data transmission at the time when 24 bits have elapsed after the change of the I line indicating communication enabled in the line interface signal line is as follows. When the I line changes from OFF to ON, a timer value of 24 bits which is predetermined for the I line is set in the timer. The timer is started by setting this timer value and generates an output when 24 bits have elapsed. Then, when this output is generated, the data can be transmitted. Further, time monitoring for other line interface signals on the same line is similarly performed by appropriately changing the timer value and setting it in the timer.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention. The timer monitoring circuit 1 according to the present embodiment is a transmission / reception clock generation unit 23 provided for each line of the communication control device shown in FIG.
It is provided to be added every time. Timer monitoring circuit 1
Includes a programmable timer 11, differentiating flip-flops (F / F) 12a and 12b, a time-up interrupt latch flip-flop 13, and an AND gate 14. The CLK terminal of the programmable timer 11 has a transmission / reception clock d that matches the communication speed generated by the transmission / reception clock generation unit 23.
To receive. The data input a of the programmable timer 11 is
The timer counter value output from the control unit 24 shown in FIG. 3 is received. The programmable timer 11 starts the timer operation when the timer counter value is input from the data input a, and the transmission / reception clock d corresponding to the input timer count value.
At the time when (that is, the number of bits of transmission / reception data) is counted, a low-level timer output h for one clock of the transmission / reception clock d is output from the OUT terminal. The differentiating flip-flops 12a and 12b and the AND gate 14 make the timer output h a pulse for one cycle of the sample clock f. The time-up interrupt latch flip-flop 13 receives the pulse of the period of the sample clock f output from the AND gate 14, and holds the time-up interrupt g until the reset signal g is supplied.

Here, the timer counter value supplied to the programmable timer 11 is stored in the local memory 25 shown in FIG. FIG. 2B is a diagram showing a storage state of the timer count value in the local memory 25. The timer counter value is stored in a table format for each line. A plurality of timer counter values are prepared for each line. That is, a unique timer counter value is prepared for each line interface signal that requires monitoring for a specified time.
The transmission / reception clock generation unit 23 normally generates the transmission / reception clock C which is 16 times or 32 times the communication speed of the line, but the transmission / reception clock C is not directly related to the circuit operation of this embodiment.

Next, the circuit operation of this embodiment will be described with reference to the operation timing chart of FIG.

Now, assume that the timer monitoring circuit 1 shown in FIG. 1 relates to the line # 0 shown in FIG. 3, and the object to be monitored is the I line of the line interface signal lines as shown in FIG. 6 described above. It is assumed that it is the specified time monitoring.

The line # 0 transmission / reception control unit shown in FIG. 3 monitors the state of the I line. When the I line is turned from OFF to ON, the line # 0 transmission / reception control unit detects this change and notifies the processor unit 26 of the control unit 24 of it. Upon receiving this notification, the processor unit 26 refers to the local memory 25, and the I of line # 0
Read the timer counter value (24 _{(10) in} this case) for the line. The timer count value 24 ₍₁₀₎ of the read I line is supplied to the data input a of the programmable timer 11 shown in FIG. 1 under the control of the processor unit 26. Programmable timer 11 uses data input a to timer counter value 24
Input ₍₁₀₎ to start the timer operation (Fig. 2 (a))
(A), (b)). When the programmable timer 11 counts the set timer count value 24 ₍₁₀₎ , it outputs a low-level timer output h ((a) and (b) in FIG. 2 (a)). When this timer output h is output,
Due to the action of the differential flip-flops 12a and 12b, the inputs 1 and 2 of the AND gate 14 are respectively shown in FIG. 2 (a).
Change as described in (d) and (e). Therefore, the AND gate 14 transmits / receives the clock d ((a) in FIG. 2 (a)).
A pulse for one cycle of the sample clock f ((c) in FIG. 2 (a)) having a faster cycle (pre-differential output:
This pulse is obtained by pre-differentiating the timer output h with the sample clock f) ((f) in FIG. 2 (a)). The time-up interrupt latch flip-flop 13 receives the pulse of the AND gate 14,
A time-up interrupt g is output ((g) in FIG. 2 (a)). Then, when this time-up interrupt occurs, the control program executes a predetermined time-up interrupt process. The time-up interrupt sends the reset signal e to the time-up interrupt latch flip-flop 13
It can be reset by typing in.

As described above, the time monitoring for the specified time of the I line is performed. Further, the control of the RS signal which is the line interface signal at the time of connecting the modem and the other signals can be realized in the same manner.

As described above, according to the present embodiment, the time monitoring of each line interface signal line depending on the communication speed can be realized only by providing one timer monitoring device for each line. Also,
According to the present embodiment, it is apparent that the fixed time monitoring that does not depend on the communication speed can be performed. In this case, conventionally, one timer common to all the lines was used and the timer monitoring state of all the lines was determined each time a time-up interrupt of the timer occurred, but when this embodiment is applied Since only the time-up interrupt is generated from the line that is monitoring the timer, it is possible to reduce the load of the time-up process on the operation of the device.

(Effects of the Invention) As described above, according to the present invention, one timer monitoring circuit is provided for each line, and an arbitrary time length in 1-bit units can be set to monitor the time of each line interface signal line. Since it was decided to do so, compared to the conventional method in which a hardware counter circuit with a fixed timer count value was provided for each line interface signal line in order to satisfy the time regulation that depends on the communication speed, the time monitoring capability is reduced. It is possible to provide an economical timer monitoring method that requires less hardware. Moreover, the present invention can be effectively applied to time monitoring of a fixed time irrelevant to a communication device.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 (a).
Is an operation timing chart of this embodiment, FIG. 2 (b) is a diagram showing the contents of the local memory in this embodiment, FIG. 3 is a block diagram of one configuration example of the communication control device, and FIG. FIG. 5 is a timing chart for explaining the regulation of an unrelated fixed time, FIG. 5 is a diagram showing the contents of the local memory in the conventional method, FIG. 6 is a diagram showing an example of the time regulation depending on the communication speed, and FIG. FIG. 8 is a circuit diagram showing conventional hardware for obtaining the time regulation shown in FIG. 6, FIG. 8 (a) is a diagram showing another example of the time regulation depending on the normal speed, and FIG. It is a circuit diagram which shows the conventional hardware for obtaining the time regulation of Fig.8 (a). 1 ... Timer monitoring circuit, 11 ... Programmable timer, 12a, 12b ... Differentiation flip-flop, 13 ... Time-up interrupt latch flip-flop, 14 ... And gate, 21 ... Communication control device, 22 ... Common timer, 23 …… Transmission / reception clock generation section, 24 …… Control section, 25 …… Local memory (LM), 26 …… Processor unit (PU).

Claims (1)

[Claims] 1. A transmission / reception control unit, which is provided for each line and controls transmission / reception of the line, in a communication control device having a monitoring function for monitoring whether or not a line interface signal satisfies a prescribed time in a communication protocol. A transmission / reception clock generation unit that is provided for each line and supplies a transmission / reception clock to the transmission / reception control unit; and a transmission / reception clock that is provided for each line and that is output from the transmission / reception clock generation unit counts as a basic clock, and An arbitrary timer value can be set, a timer circuit that outputs a time-up signal when time counting according to this timer value is performed, and a timer value that is set in the timer circuit is set for each line and for each line interface signal. And a memory for storing the line interface signal to meet the specified time on the communication protocol. If it is monitored whether or not the line interface signal is read, the timer value corresponding to the line interface signal is read from the memory and set in the timer, and then it is detected whether or not the timer has timed out and the line interface signal is detected. A communication control device characterized in that it is monitored whether or not the specified time on the communication protocol is satisfied.