JPS5951166B2 - Width increase circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an amplifier circuit comprising a vertical junction field effect transistor for providing an input signal.

Conventionally, bipolar transistors have been used in various electronic devices such as audio amplifiers, and these are current control elements that perform amplification by controlling minority carriers.

Bipolar transistors have low input resistance, and
It has drawbacks such as poor switching characteristics.

On the other hand, recently, vertical junction field effect I transistors (
(hereinafter simply referred to as V-FET) was developed.

As described below, this V-FET has characteristics suitable for use in audio amplifiers and the like.

That is, (1) good pulse response characteristics.

(2) Complementary characteristics of N channel and P channel can be obtained.

(3) Smooth pitch and pitch characteristics.

(4) Lee's output impedance and high input impedance.

(5) It is a voltage responsive element.

It has the following characteristics.

In an audio amplifier or the like constructed using a V-FET, the frequency characteristics are flat up to the high range, making it possible to obtain so-called crisp reproduced sound.

Furthermore, an audio amplifier or the like constructed using a v-FET has high input impedance and low output impedance, resulting in an audio amplifier with high sensitivity and low distortion.

Furthermore, since the push-pull amplifier circuit constructed using V-FETs has good complementary characteristics, no special phase inversion circuit is required.

Next, an example of a V-FET having the above-mentioned characteristics was
This will be explained based on FIGS.

First, the structure of a V-FET will be described. As shown in FIG. 1, a V-FET chip 1 is provided with a large number of source regions 3, for example, about 1,500, separated by a thick oxide film 2. .

These source regions 3 are connected in parallel to source metal electrodes 4, respectively.

On the other hand, a gate region 6 is formed in the semiconductor substrate 5. The gate region 6 includes a frame-shaped portion 6a and a net-shaped portion 6b integrally formed within the frame-shaped portion.

A gate I metal electrode 7 is connected to the frame portion 6a, and the source region 3 is provided in a portion corresponding to each mesh of the net portion 6b.

Further, 8 indicates a drain region. V with this kind of structure
-FET, the current flowing in the vertical direction with respect to the semiconductor substrate 5, that is, between the source region 3 and the toluin region 8, is controlled in the horizontal direction by the gate region 6.

Next, the operation and output characteristics of the above-mentioned V-FET will be described.

V-FETs are generally symbolized as shown in FIG. 2 Q1, where source S indicates a terminal connected to source metal electrode 4, gate G to gate metal electrode 7, and drain D to drain region 8. The terminal shown is connected to the terminal.

A predetermined voltage V is applied between the gate and the source.

5 is supplied, and a predetermined voltage VDS is supplied between the drain and source.

Note that VDD represents the power supply voltage, and resistor RL represents the load resistance of this circuit.

Now suppose that the gate-source voltage VGS is a constant voltage E
i (negative polarity voltage), and in this state, the drain-source voltage VDS is continuously changed from OV to a high voltage.

Along with this, the current ID flowing through the V-FET Ql also gradually increases, and the output characteristic E1 shown in FIG. 3 is obtained.

Next, the voltage between the gate and source ■.

5 to a voltage E5 higher in the negative polarity than E1, and in this state, the drain-source voltage VDS is continuously changed from OV to a high voltage.

At this time, the current flowing through V-FETQl is ■. is the drain
There is no current that brings the source-to-source voltage VDS to a predetermined voltage (■0).

Then, the drain-source voltage VDS is a predetermined voltage V
As the value gradually increases from o, the current ID gradually increases, and an output characteristic E2 shown in FIG. 3 is obtained.

These output characteristics E1. As is clear from FIG. 3, E2 exhibits so-called triode characteristics.

In the case of such triode characteristics, the power supply voltage VDD and the gate-source voltage ■.

5 changes, the current I.

is also subject to large fluctuations. That is, now the power supply voltage V
If DD changes and the drain-source voltage VDS changes from ■1 to ■2 shown in FIG. 3, the current ID also changes from ■1 to ■2.

At this time, as shown in FIG. 3, the current flow rate varies depending on the fluctuation of the drain-source voltage VDS.

fluctuation becomes large.

Therefore, the operation of the V-FET having triode characteristics has the disadvantage that it tends to become unstable due to fluctuations in the power supply voltage VDD.

Further, in push-pull amplifier circuits using V-FETs, crossover distortion tends to occur when the drain-source voltage VDS fluctuates.

SUMMARY OF THE INVENTION The present invention is intended to correct the above-mentioned deficiencies. and a constant voltage circuit for regulating the voltage between the drain and source of the FET, and the drain is connected between the base and emitter of the bipolar transistor and between the source via the constant voltage circuit.

According to the amplifier circuit configured in this way, if the power supply voltage is higher than the operating voltage of the constant voltage circuit, the current flowing through the V-FET remains constant without being affected by fluctuations in the power supply voltage. , and also has a high breakdown voltage between source and drain.
- There is no need to use FETs, and the output impedance and input impedance are high, the frequency characteristics are good, and the degree of multiplication is large.

Next, one embodiment of the amplification circuit of the present invention will be described based on FIGS. 4 to 6B.

First, the circuit configuration will be described with reference to FIG. 4. For example, N
The channel V-FETIO and the NPN bipolar transistor (hereinafter simply referred to as an L-transistor) 11 constitute a cascade amplifier circuit.

An input signal to this amplifier circuit, for example an audio signal, is supplied to the gate of the V-FETIO via the input terminal 12.

In addition, V-FETIO is a source follower, and its source is the ground line E, which is the reference potential of this amplifier circuit.
is connected to the resistor R1 via a characteristic R1, and the output signal of this amplification circuit is obtained from both ends of the resistor R1.

By the way, the source of V-FETIO is connected to the resistor R1 as described above, and is also connected to one end of the Zener diode Dz.

The other end of the Zener diode Dz is connected to the base of the transistor 11 and one end of the resistor R2.
Connected to power line.

Therefore, the base current of the transistor 11 is supplied via the resistor R2, and the current flowing through the resistor R2 also flows to the ground line E via the Zener diode Dz and the resistor R1.

Based on this current, a Zener voltage Vz is obtained from both ends of the Zener diode D2.

Next, the circuit operation of the amplifier circuit shown in FIG. 4 will be explained.

First, the output characteristics of the amplifier circuit will be described.

V - Voltage V between the gate and source of FETIO.

5 to a predetermined voltage, and in this state, the 10B power supply voltage is continuously changed from OV to high voltage.

As a result, current ■1 flows from 10B power supply in → resistor R2 → Zener diode Dz resistor R1 → earth line E,
This current value increases as the 10B power supply voltage increases.

At the same time, a resistor R is connected to the base of the transistor 11.
Since the base current is supplied through the terminal 2, the current ID also flows from the 10B power supply in to the transistor 11 to the V-FETIO to the resistor R1 to the ground line E.

The current value of the current ID increases rapidly as the 1B power supply voltage increases, as shown in output characteristic A shown in FIG.

Further, this current ID increases based on the triode characteristics of the y-FETIO, and becomes a current amplified by the current amplification rate hfe of the transistor 11.

Next, when the '+B power supply voltage is continuously changed from Ov to a high voltage, the voltage Vns between the drain and source of V-FETIO and the voltage drop between the base and emitter of transistor 11, for example, about 0.6V, are changed. The sum voltage becomes equal to the Zener voltage Vz.

In this state, when the 10B power supply voltage is continuously changed to a higher voltage, the above-mentioned current 11 increases accordingly.

However, the voltage VD between the drain and source of V-FETIO
Since S is regulated to a predetermined voltage by the action of the Zener diode Dz, the current p flowing through the V-FETIO has a constant current value.

That is, the current ■.

As shown in characteristic A in FIG. 5, the current value increases rapidly between the 10B power supply voltage Ov and the Zener voltage vz, and becomes equal to the current value above the Zener voltage Vz.

and the voltage V between the gate and source of V-FETIO.

By setting S to a voltage higher in the negative polarity direction than the above voltage, 10B
When the power supply voltage is changed in the same manner as in the case described above, one current flows as shown by characteristic B in FIG.

Similarly, if the voltage Vcs between the gate and source of V-FETIO is sequentially switched to lower voltages, and the 1B power supply voltage for each voltage is continuously changed from Ov to a higher voltage, the corresponding Obtain characteristics C, D, and E.

In this way, the output characteristic of the amplifying circuit described above becomes a pentode characteristic as shown in FIG.

Therefore, the 10B power supply voltage is set to a voltage value corresponding to, for example, Vp in FIG.
If the amplification circuit performs the amplification operation, the current ID will hardly change even if the power supply voltage changes to some extent.

Next, the amplification operation of this amplification circuit will be described.

First, the power supply voltage is set to a voltage corresponding to Vp, and then V-F
Initial voltage between gate and source of ETIO■.

For example, so is set to a voltage value of characteristic C. In this state, when the input signal vi of the audio signal is supplied to the input terminal 12, the voltage VGS between the gate and source of the V-FET 10 has a waveform in which the input signals are superimposed, as shown in FIG.

First, when the input signal vi has a positive polarity from 0 to θ1, the voltage VGS between the gate and source of V-FETIO becomes high, so the current .

will increase.

Therefore, the voltage across the resistor R1, that is, the source voltage e of the V-FET is also the initial voltage e.

6B.

Then, the source voltage of the V-FETIO and the voltage at one end of the Zener diode Dz increase by a change v1 in the voltage e.

On the other hand, since the Zener voltage Vz is always constant, the emitter and base voltages of the transistor 11 are increased by the aforementioned change (1).

However, since the 10B power supply voltage is fixed at Vp, the voltage across the resistor R2 becomes low, and at the same time, the voltage between the collector and emitter of the transistor 11 becomes V.

E becomes lower by the voltage change V1 mentioned above.

During the negative polarity of the input signal vi from θ to θ2, the voltage VGS between the gate and source of V-FETIO
This means that the current 0 is also reduced.

Therefore, the voltage e across the characteristic R1 also changes as shown in FIG. 6B.

Then, the source voltage of the V-FETIO and the voltage at one end of the Zener voltage Dz are lowered by the change in voltage e by 2.

On the other hand, since the Zener dummy voltage vz is always constant, the emitter and base voltages of the transistor 11 are lowered by the above-mentioned change amount V2.

However, since the 10B power supply voltage is fixed at Vp, the voltage across the resistor R2 increases, and at the same time, the voltage V between the collector and emitter of the transistor 11 increases.

E increases by the amount of change v2 mentioned above.

Thereafter, the above-described operation is performed in response to the voltage change of the input signal vi, and the voltage e across the resistor R1 is obtained as the output signal of this amplification circuit.

Note that while the above-described operation is being performed, even if the power supply voltage Vp fluctuates to a certain extent, the collector-emitter voltage V of the transistor 11 remains constant.

Although E changes, the voltage VDS between the drain and source of V-FETIO does not change, so the current is ■.

never fluctuates.

Next, a class B push-pull power amplification circuit to which the amplification circuit of the present invention is applied will be described as a second embodiment with reference to FIGS. 6 and 7.

Note that the same reference numerals are given to the parts that operate in the same way as in the first embodiment, and the explanation thereof will be omitted.

One circuit block A of the class B push-pull power amplification circuit shown in FIG. 7 uses the amplification circuit shown in FIG. 4 described above as is.

Further, circuit block B is constructed by reversing the polarity of voltage block A between sources, and this circuit block B
In this case, the V- of the P channel supplied with the input signal is
The FET 20 and the PNP transistor 21 constitute a cascade amplifier circuit.

Note that the Zener diode Dz' has the same function as the Zener diode Dz described above, and has a resistor R1.
□ is the resistance R2 mentioned above, and resistance R1 □ is the resistance R mentioned above.
It works in the same way as 1.

Further, since the circuit block B is for amplifying the negative half-wave of the input signal supplied via the input terminal 22, the collector of the transistor 21 is connected to the -B power supply line.

One end of the resistor R1 and one end of the resistor R1 are connected to this B
They are commonly connected to one end of a load of the class push-pull power amplification circuit, for example, a speaker Sp.

Therefore, the positive polarity output signal obtained from circuit block A and the negative polarity output signal obtained from circuit block B are as follows.
The circuit blocks A and B are combined at a connection point O to drive a load such as a speaker Sp.

Note that the resistor R6 is a protective resistor for the speaker and each circuit block A, B.

Next, describing the output characteristics of each circuit block A and B, as for circuit block A, as described above,
The output characteristic α shown in FIG. 8 is obtained.

For convenience of explanation, the current flowing through circuit block A is referred to as ID
Let it be a.

In addition, the output characteristic β of circuit block B is determined by setting the voltage VGS between the gate and source of the V-FET 20 as a positive voltage, and setting the voltage between the drain and source as -B voltage. It is obtained by increasing the polarity continuously from OV in the negative polarity direction.

For convenience of explanation, the current flowing through circuit block B is I.

b. Note that the output characteristics α and β are pentode characteristics that are symmetrical to each other.

On the other hand, the output characteristic γ of the entire B-class push-pull power amplification circuit is
is obtained by combining the output characteristic α and the output characteristic β.

That is, the current IDa flowing through the circuit block A and the current Db flowing through the circuit block B have the same supply value and opposite polarities.

The above-mentioned current ■Da and current Inb flow through the connection point O.

Therefore, the current at the connection point O is the sum of the currents IDa and IDb, and when their absolute values are equal, the current value becomes zero.

When the sum of the currents IDa and IDb is determined in this way, the output characteristic γ of the linear-class push-pull power amplification circuit as shown in FIG. 8 is obtained.

Then, the operating point P of the output characteristic γ is determined on the straight line part,
Moreover, by finding the desired load line, it is possible to ideally increase the width.

A sinusoidal continuous human input signal (not shown) is then passed through the input terminal 12.22 to the V-FETIO.

The circuit operation when the signal is supplied to each of the 20 gates G will be described.

First, when a positive half wave is supplied, only circuit block A operates and circuit block B does not operate.

The current IDa of the circuit block A flows from the contact O to the ground line E via the speaker and the resistor Ro.

Further, when the sine wave input signal is a negative half wave, only circuit block B operates and circuit block A does not operate.

The current IDb of the circuit block B flows from the connection point O to the ground line via the speaker Sp and the resistor R8.

Therefore, the positive and negative half-waves of the input signal are individually amplified to form a combined output signal at contact O.

Therefore, the speaker Sp will be driven regardless of which of the circuit blocks A and B is in operation.

In this way, by circuit block B having pentode characteristics, B
If a class push-pull power amplification circuit is configured, the current at the operating point P will not change even if the power supply voltage fluctuates.

Therefore, it is possible to prevent the occurrence of crossover distortion that tends to occur when the output signals obtained from each circuit block A and B are combined.

Here, we will discuss crossover distortion in the class B push-pull power amplification circuit.

Crossover distortion is the distortion that occurs at the zero cross position when the positive half-wave of the output signal obtained from circuit block A and the half-wave of the output signal obtained from circuit block B are combined at connection point O. be.

That is, in conventional class B push-pull power amplification circuits, when the positive half-wave of the input signal is generally amplified, if the operating point of circuit block A changes, the amplification is no longer performed at a predetermined degree of amplification. .

For this purpose, the output signal of circuit block A and the output signal of circuit block B
When combining the output signals of , a time gap occurs between the zero cross positions of both, and an output signal with a waveform different from that of the input signal occurs between the positive output signal and the negative output signal. is obtained.

Conversely, a positive output signal and a negative output signal may overlap near the zero cross position, resulting in an output signal having a waveform different from that of the input signal.

However, as described above, in the amplifier circuit having pentode characteristics, the operating point P is stable, so crossover distortion is unlikely to occur.

Therefore, an output signal with little distortion can be obtained with stable operation at all times.

As described above, the present invention provides a V-F for supplying input signals.
It consists of a bipolar transistor connected in cascade to the ET, and a constant voltage circuit for regulating the voltage between the drain and source of the V-FET, and the drain is connected between the base and emitter of the bipolar transistor and the constant voltage circuit. It is connected to the source via a voltage circuit.

Therefore, according to the amplifier circuit configured in this way, when the power supply voltage reaches the operating voltage of the constant voltage circuit, the voltage between the drain and source of the V-FET is kept constant even if it exceeds the operating voltage. Since it can be held constant by the circuit, V-FE
The current flowing through T can be kept constant.

In addition, even if the power supply voltage fluctuates slightly, the voltage between the drain and source of the V-FET is kept constant by the constant voltage circuit, so fluctuations in the power supply voltage may make the operation of the amplifier circuit unstable. Furthermore, there is no need to use a V-FET with high withstand voltage between the drain and source, and production costs can be reduced.

Also, since the input signal was supplied to the V-FET,
Lee's output impedance, high input impedance, and good frequency characteristics can be obtained.

Furthermore, since a bipolar transistor is cascade-connected to the V-FET, a large degree of increase can be obtained.

[Brief explanation of drawings]

Figures 1 to 3 show the structure and output of a vertical junction field effect transistor, with Figure 1 being an enlarged sectional view showing the structure, and Figure 2 being a circuit diagram for explaining circuit operation. ,
FIG. 3 is an output characteristic diagram. 4 to 6 show the first embodiment of the present invention, in which FIG. 4 is a circuit diagram, FIG. 5 is an output characteristic diagram, and FIGS. 6A and 6B explain the circuit operation. FIG. 7 and 8 show a second embodiment of the present invention, in which FIG. 7 is a circuit diagram and FIG. 8 is an output characteristic diagram. In addition, in the symbols used in the drawings, 10 is a vertical junction field effect transistor, 11 is a bipolar transistor, (VDs) is the voltage between the drain and source,
(VGS) is the voltage between the gate and source, and (Dz) is the Zener diode.

Claims (1)

[Claims] 1 A vertical junction field effect transistor for supplying a human power signal, a bipolar transistor connected in cascade to this field effect transistor, and a constant voltage for defining the voltage between the drain and source of the field effect transistor. and a voltage circuit, the amplification circuit having the drain connected to the source via the base-emitter of the bipolar transistor and the constant voltage circuit.