JPS5951179B2 - semiconductor latching relay - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor latching relay with a set input signal storage function.

Conventionally, solid-state relays made of a combination of semiconductor elements are known, and this type of relay is reset when all power is cut off, and reapplies the set input signal when the power is turned on again. Must.

In view of the above circumstances, this invention provides a solid state relay with a set input memory function, so that even if all power is cut off during an accident such as a power outage, it will be automatically set and returned to its original state when the power is restored. The purpose is to provide semiconductor latching relays that can be obtained.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, in which a pair of AC terminals P1... to which an AC power source E is connected via a load RL. A bidirectional switching element TRA such as a TRIAC is connected between P2.
A single-phase full-wave rectifier circuit RC is connected between the gate and second electrode of this element TRA, and a thyristor SCR and an oscillation circuit O8C are connected to the DC terminal of this circuit RC.

The oscillation circuit O8C constitutes a Colpitts oscillation circuit including, for example, an oscillation output take-out coil L1 wound around the memory core MC, a resistor R1°R2, capacitors C1 to C3, and a transistor TR1.

The memory core MC includes a set input coil L2 that magnetizes the core to a high level upon application of a set input signal a, a reset input coil L3 that magnetizes or demagnetizes the memory core MC to a low level when a reset input signal is applied, and a memory core MC. A detection coil L4 for detecting a change in the oscillation output based on a change in the magnetization of the transistor T is connected to the base of the switching transistor TR2 via a diode D for preventing backflow.
Application of an ignition signal to the gate pole of the SCR is controlled by turning R2 ON and OFF.

Next, the operation of the above configuration will be explained.

When there is no set input signal a and the memory core MC is not magnetized, the oscillation output of the oscillation circuit O8C causes the coil L to
1 to generate an alternating magnetic field within the memory core MC.

As a result, an induced electromotive force is generated in the detection coil L4, and the transistor TR2 is turned on via the diode D.
The gate pole of the SCR is shorted and does not turn on the SCR.

Therefore, element TRA is OFF, and no current is applied to load RL.

In this state, when set input signal a is applied, memory core MC is excited and saturated through set input coil L2, and oscillation of oscillation circuit O8C stops, so that induced electromotive force is generated in detection coil L4. No occurrence, transistor TR2
is turned off, the gate electrode of the SCR is energized from the resistor R4, this SCR is fired, and when the element TRA is turned on, the load RL is energized.

Even if power is cut off from the power supply E due to some accident during this energization, the saturation magnetization of the memory core MC will remain as it is, so when the power supply E is turned on again, the set input signal a will not be applied. However, the oscillation circuit O8C is still stopped,
Therefore, TR2 is turned off, SCR and TRA are turned on, and power supply to the load RL is restarted.

That is, the memory core MC performs a storage operation for the set input signal a.

Note that when a reset input signal is applied to the coil L3, the core MC is reverse excited and demagnetized, the oscillation circuit O8C starts oscillation, cuts off the current supply to the load RL, and returns to the initial state.

As mentioned above, this invention allows even if the power is cut off,
Since the memory core remembers the application of the set input signal, when the power is turned on again, the previous state can be restored, and the function as a latching relay in a magnetic relay can be achieved.

In addition, compared to magnetic relays, they are more resistant to external disturbances such as vibrations and shocks, and on the other hand, they are not affected by arcs, noise, etc., which are the advantages of solid state relays.

[Brief explanation of the drawing]

FIG. 1 is an electric circuit diagram showing an example of a semiconductor latching relay according to the present invention. MC...Memory core, Ll...Oscillation output take-out coil, L2...Set input coil,
L3...Reset input coil, L4...
・Detection coil, O8C...Oscillation circuit.

Claims (1)

[Claims] 1 a memory core, a set input coil that magnetizes the memory core to a high level upon application of a set input signal, and a reset input coil that magnetizes or demagnetizes the memory core to a low level;
an oscillation circuit that applies an oscillation output to the memory core and stops oscillation when the memory core is excited and saturated; a detection coil that detects a change in the oscillation output based on a change in magnetization of the memory core; A semiconductor latching relay comprising a switching circuit that controls ON and OFF of a load in response to a detection signal from a coil.