JPS5951187B2 - Fault detection method for data receiving equipment - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a failure detection method for a data receiving device, and more particularly to a failure detection method for a data receiving device that receives data in a time-division manner.

Background of the Technology Generally, when data is transmitted from a transmitting side such as a wide processing device to a receiving side such as a line controlling device in a data line control device, etc., the data being sent includes access to the device that should receive the data. Contains control data for

In this case, if a failure occurs on the receiving device side, there is a risk that data will be erroneously transmitted to a device other than the device to which the data should be transmitted. Therefore, in the above-mentioned transmitting/receiving device, the presence or absence of a failure on the receiving device side is detected before forwarding the message to another device, and if a failure is detected, access by other devices is prohibited. There is a need to. Prior Art and Problems An example of a fault detection method for a conventional data receiving device is shown in FIG.

In the circuit diagram of FIG. 1, 1 is a transmitting device and 2 is a receiving device. Between the transmitting device 1 and the receiving device, there are synchronizing signal lines SYNC, L and data sending lines DATA, 1 to D.
ATA, 32 is connected.

In the transmitting device 1, a data signal from the data forming circuit 11 is transmitted to the receiving side via the transmitting circuit 12.
In the receiving device 2, the signal transmitted from the transmitting side is
The signal is input to the receiving circuit 21. In the transmitting/receiving device shown in Fig. 1, the f-bit from the transmitting side is transmitted at a time via a 32-bit f-bit sending line, and is added to the transmission data and transmitted via a synchronization signal line. The synchronized clock signal is read into the register circuit 22 of the receiving device 2.

Of the 32-bit data transmission line, the upper 16 bits are the contents of the transmission data, and the lower 16 bits are control data for accessing the device to which the data is to be transmitted.

Therefore, the upper 16 bits of data are sent to the data distribution circuit 23.
The lower 16 bits are input to the decoder circuit 25 via the delay circuit 24. In the decoder circuit 25, the transmitted control data is analyzed and a signal for selecting the device to be accessed is output. Consider a case where a failure occurs in the receiving device 2 of FIG. 1.

When the transmission data is transmitted, the 32-bit data on the sending line is read into the reregister circuit 22 by the synchronous clock signal. However, since the control data is connected to the decoder 25 via the delay circuit 24, at the time the synchronous clock signal is input, the data input to the decoder 25 is in a state where no device is selected. Therefore, both output lines of the decoder 25 should be in the off state. All output lines of the decoder 25 are
The signal is input to the NOR gate circuit 26, and the output of the NOR gate circuit 26 is inputted to the register circuit 27. Register circuit 27
Since the input is read by the synchronous clock signal, data "1" is output from the register circuit 27 under normal conditions. However, if the receiving device 2 is in trouble, one of the output lines of the decoder circuit 25 may be turned on even when none of the devices is selected, and therefore the register Data “0” is read into the circuit 27. Follow. And gate circuit 2
8, the output of signals for accessing the device is prohibited. In this way, in the apparatus shown in FIG. 1, the detection of a fault in the receiving device is carried out simultaneously with data reception using the synchronous clock signal, and the occurrence of the fault is detected. If detected, access to the device on the receiving side is prohibited.

By the way, in the above-mentioned fault detection method, since data reception and fault detection are performed at the same time, it is necessary to delay the received data in order to prevent invalid operation on the receiving device side.
In addition, recently, a transmission method that divides data into control data and content data and sends them out in a time-sharing manner has become commonly used, and in this case, applying the above-mentioned failure detection method can prevent device access from occurring. The problem is that there is a delay.

OBJECTS OF THE INVENTION In view of the problems of the conventional type described above, the main object of the present invention is to reduce the number of data transmission lines as much as possible and to use the transmission lines in a time-sharing manner to transmit and receive data. It is an object of the present invention to provide a fault detection method for a data receiving device that can detect a fault on the receiving device side without delay.

Structure of the Invention In the present invention, in a failure detection method for a data receiving device between devices that transmit and receive data, the data receiving device connects first and second synchronization signal lines and a data transmission line between the data receiving device and the transmitting device. a receiving circuit connected to the receiver circuit, two register circuits each receiving the outputs of the receiving circuit, a data distribution circuit connected to one register circuit of the register circuit, and a data distribution circuit connected to the other register circuit of the register circuit. a decoder circuit connected to the register circuit of the register circuit, and a detecting means for detecting a fault based on the output signal of the decoder circuit; reading data in the register circuit and outputting it to the data distribution circuit, and operating the detection means by the first synchronous clock signal;
The second synchronous clock signal sent via the second synchronous signal line causes the other register circuit to read data and output it to the decoder circuit, and
When receiving the second synchronous clock signal, the detecting means detects a fault based on the output state of the decoder circuit, and when the fault is detected, the detecting means detects the fault with respect to the subsequent data sent by the second synchronous clock signal. A failure detection method for a data receiving device is provided, which is characterized by inhibiting output from a decoder circuit.

Embodiment of the Invention As an embodiment of the present invention, a failure detection method for a data receiving device will be explained below using the transmitting/receiving device shown in FIG.

The apparatus shown in FIG. 2 is composed of a transmitter 3 and a receiver 4, and between the transmitter 3 and the receiver 4 are first and second synchronization signal lines SYNC. 1 and SYNC. 2, and a 16-bit data transmission line DATA. 1~DATA
．． 16 are connected. In the transmitting device 3, a data signal from a data forming unit 31 such as a central processing unit is transmitted to a receiving circuit 41 of the receiving device 4 via a transmitting circuit 32.

The data transmitted from the transmitting device 3 consists of two sets of data.
The data is divided into 16 bits and sent out in batches. The first 16 bits transmitted are the contents of the transmission data and are sent simultaneously with the synchronization clock signal on the first synchronization signal line.
Each output of the receiving circuit 41 to which data is input is input to two register circuits 42, and one register circuit 42 is connected to the first synchronizing signal line SYNC. The other register circuit 42 is read by the synchronization clock signal from the second synchronization signal line SYNC.1. It is read by the synchronous clock signal from 2. Therefore, the first transmitted data is read into the register circuit 42 by the synchronization tarlock signal on the first synchronization signal line, and is then read into the data distribution circuit 42.
3 is input.

The output of the register circuit 42 read in response to the synchronous clock signal on the second synchronous signal line is input to a decoder circuit 44. At the time when the synchronous tarlock signal on the first synchronous signal line is sent, the input of the decoder circuit 44 has not been read, and the state of the input is different from that of the decoder circuit 44.
The output from 4 is reset so that it does not access any devices. All of the output lines of the decoder circuit 44 are input to the NOR gate circuit 45, and the output of the NOR gate circuit 45 is "1" only when all five output lines are off, and "1" in other cases. 0". The output of the NOR gate circuit 45 is input to a register circuit 46, and is read in the register circuit 46 by the synchronization clock signal on the first synchronization signal line. If there is no failure in the receiving device 4, all outputs of the decoder circuit 44 are off at the time when the synchronization clock signal of the first synchronization signal line is input, as described above, and the output of the lino gate circuit 45 is It is "1".

Therefore, data "1" is read into the register circuit 46. The output of the register circuit 46 is input to one input of each AND gate circuit 47 . AND gate circuit 47
The output of the decoder circuit 44 is input to the other input of each one. Therefore, if there is no failure in the receiving device 4, the decoder circuit 4
Four output signals are transmitted to each device. Assuming that one of the outputs of the decoder circuit 44 is always on when there is some kind of failure in the receiving device 4,
Data “0” is read into the register circuit 46.

Therefore, the fault is detected in the register 46, and the AND gate circuit 47 prohibits the output of the decoder circuit 44 from being transmitted to other devices. In this way, in the apparatus shown in FIG. 2, the presence or absence of a fault in the receiving device 4 is detected at the time when the synchronizing clock signal on the first synchronizing signal line is input. Next, the 16-bit control data is transmitted from the transmitting device 3 to the receiving device 4 along with the synchronized tarlock signal on the second synchronizing signal line, read into the register circuit 42, and inputted into the decoder circuit 44.

The decoder circuit 44 outputs a signal for accessing the device specified by the input control data.
At this point, fault detection in the receiving device 4 has already been performed, so if no fault exists, the output of the decoder circuit 44 is transmitted to each device via the AND game circuit 47, and the designated device can be accessed. Effects of the Invention According to the present invention, in a transmitting/receiving device that transmits a set of data in a time-division manner, a failure on the receiving device side can be detected without delaying control data.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a transmitting/receiving device using a conventional failure detection method for a data receiving device, and FIG. 2 is a circuit diagram of a transmitting/receiving device using a failure detecting method for a data receiving device as an embodiment of the present invention. It is a diagram. Explanation of symbols, 1... Transmitting device, 2... Receiving device, 3
... Transmitting device, 4... Receiving device, 11... Data forming section, 12... Transmitting circuit, 21... Receiving circuit, 2
2... Lujistor circuit, 23... Data distribution circuit, 24
...Delay circuit, 25...Decoder circuit, 26...
Noah gate circuit, 27...Register circuit, 28...
AND gate circuit, 31... De-gate forming section, 32...
- Transmission circuit, 41... Receiving circuit, 42... Logistor circuit, 43... Data distribution circuit, 44... Decoder circuit, 45... Noah game circuit, 46... Register circuit, 47...・And game circuit.

Claims (1)

[Claims] 1. In a failure detection method for a data receiving device between devices that transmit and receive data, the data receiving device has a receiving circuit connected to the transmitting device by first and second synchronization signal lines and a data transmission line. , two register circuits each inputting each of the outputs of the receiving circuit;
A data distribution circuit connected to one of the register circuits, a decoder circuit connected to the other register circuit of the register circuits, and a detection means for detecting a failure based on an output signal of the decoder circuit, In response to the first synchronous clock signal sent through the first synchronous signal line, the one register circuit reads data and outputs it to the data distribution circuit, and the first synchronous clock signal causes the detection means to read data and output it to the data distribution circuit. The second synchronous clock signal sent through the second synchronous signal line causes the other register circuit to read data and output it to the decoder circuit, and the first synchronous clock signal The detection means detects a fault based on the output state of the decoder circuit, and when the fault is detected, the detecting means detects a fault from the decoder circuit with respect to subsequent data sent by the second synchronous clock signal. A fault detection method for a data receiving device characterized by inhibiting output.