JPS5953565B2 - Direct memory access control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a direct memory access control device, and particularly to a direct memory access control device suitable for handling time-based, columnar data with multiple channels as an input/output device.

A direct memory access (hereinafter abbreviated as DMA) control device is a system that directly communicates data between a main memory and a device without going through a central processing unit.

Hereinafter, we will discuss a DMA control device when the device is multi-channel and consists of time-series data. FIG. 1 is a diagram showing the entire conventional configuration.

m channels CHI, CH2,...,CH
The m time series data are scanned individually as data via a multiplexer (MPX) 2 and sent to the DMA control device 3. This DMA control device 3 is a central processing unit (C
PU) 4 and main memory (M) 5. The timing of data A in each channel is shown in FIG. 2a, and the output B of the MPX 3 and the output C of the DMA controller 3 are shown in FIG. In the figure, it is assumed that each channel handles n pieces of data. As is clear from FIG. 2, first, the first data 1.1, 1.2, . . . , 1.m of each channel is sent.

Next, the second data of each channel 2 ・1, 2
・2, ..., 2・m are transmitted in order.
Hereafter, while repeating the same process, the nth data n
・ Send 1, n・ 2, ......, nm,
Transmission of all data across all channels is complete. After all the data is transmitted, the next whole data is transmitted in the same way. FIG. 3 is a diagram showing the internal configuration and some interface configurations of the DMA control device.

The DMA control device 3 is interposed between the input/output bus 100 and the device control circuit 200, and controls execution of data transfer between the device and the main memory. DMA control device 3
is a data receiver (REC) 11, a memory address register (MAR) 12, and a data counter (DC).
13, Command register (COM) 14, Data buffer register (BUF) 15, Address driver (DRIVER) 16, Multiplexer (MPX) 1
7. Consists of a control circuit (CTL) 18. Furthermore, the lines include an input data line (DATA) 21, a control information line (CTLC) 22, and an output line (DATA).
) 23, memory address line (ADDRESS) 24
exists and is connected to the input/output bus 100. A status input line (S
TATUS) 31, data output line (DATA) 32
, command output line (COM) 33, control input/output line (CTLC) 34, data input line (DA
TA) is intervening. First, prior to data transfer, C
The head address of the main memory to be used and the number of data transfer words are received from the PU and stored in MAR12 and DC13, respectively.

MARl2 changes its contents to A every time one word of data is transferred.
DD1 (+1), and the contents of DC13 are SUB1 (-1) every time one word of data is transferred. The data transfer ends when the content of DCl3 becomes ``0''. Let us explain the processing of multi-channel data under such a configuration.

The data captured at the timing shown in FIG. 2b are stored in the main memory in the order in which they were captured. The data arrangement of the main memory at that time is shown in FIG. When EA is set as the starting address of the main memory, as shown in the figure, the starting number: EA is data 1.], the address EA+1 is data 2.1,..., EA+( m-1)
Data m·1 is stored in . Similarly, data for each channel will be stored for each m address at the following addresses. In the end, the data shown in FIG. 2b is stored in the main memory in the order in which it is taken in, as data shown in FIG. 4. Processing of data in such an array is performed for each channel. That is, for the data of channel CH1, addresses EA, EA+ in the main memory are used.
The data of M, EA+2m, . . . , EA+(n-1)m is read out and processed as data of channel CH1. For channel CH2, address EA
+1,EA+m+1,...,EA+(n-1)
Data of m+1 is read out and processed as data of channel CH2. Thereafter, data processing for all channels is performed in the same manner. The form of data processing is determined by the nature of the data input to each channel. For example, if vibration detectors are installed at multiple locations on the shaking table in order to determine the frequency components of the shaking table, and each of the multiple vibration detectors is given a channel name, in each channel, The obtained detection signal is digitally captured, and as described above, the data is captured and stored in the main memory via the DMA control device as shown in FIG. The data captured by DMA is then read out for each channel as described above, treated as frequency analysis data for each channel, processed by FFT processing, averaging method, etc., and used for frequency characteristic detection. processing is performed. In the conventional example described above, special software must be prepared for writing to and reading from the main memory.

For example, for the data of channel CH1, it is necessary to edit discrete addresses every m, or it is necessary to edit addresses for special data distribution. In the past, such processing was taken for granted, but if you look at the process from data capture to data processing, the editing and distribution in between takes a lot of time, and the online data processing network for each channel is extremely time-consuming. It was getting hot. The present invention provides a DMA control device that makes it possible to reduce the software load and shorten processing time.

The gist of the invention is the use of fast-in, fast-out registers in place of conventional memory address registers.

Hereinafter, the present invention will be explained in detail with reference to the drawings. FIG. 5 is a diagram showing an embodiment of the present invention.

The difference from FIG. 3 is that a fast-in/fast-out register (FIFO) 19 is provided instead of MARl2.
and +1 is provided with an Add-1 circuit 20. F
IFOl9, as is well known, is a setting (input)
The data is retrieved externally (fast-out) in the order in which it is received (first-in).

In this embodiment, the word capacity of FIFO 19 is the total number of channels m. In this FIFO 19, data is stored in all words before data is taken in from each channel. This data is sent from the CPU via the data line 21. The content of the data is
These are all starting addresses for each channel. The input order of the first address is the channel order, that is, the channel CH1
, CH2, . . . , CHm. This will be explained using a specific example. The basic idea of setting addresses for each channel is that data for each channel is set in consecutive addresses.

Therefore, the start address for each channel is a discrete value. Assuming that the total number of data for each channel is n, the start address of each channel is an address obtained every n pieces. Now, if the start address of the channel CH] is FAl, then in this channel the address EAL is
It occupies addresses from address EAL+(n-1).
In the next channel CH2, address EAl+n is used as the first address, and from EAl,+n to EAl+(2n-1)
occupies the address of Channel CHi occupies addresses EAl+(11)n to EAl+i−n−]. Address EA on the last channel CHm
It occupies addresses from l+(m-1)n to EAl+m-n-1. As is clear from the above, if the start address of each channel is a continuous address for all channels, the start addresses to be set in FIFO 19 at that time are EAl, BAl+N, . ......, EAL+
(1-1)N,...,EAL+(m-1)N4
becomes. Furthermore, since the data shown in Figure 2 is fetched and used many times, the data processing is completed with only the first data, and subsequent data are set to the same address. There is no guarantee that it will be done. Therefore, in general, the first address for channel CH1 is
The start address is EAl for channel CHl,
For CH2, EA2, ..., for CHi, EAi, ..., for CHm, EAm. The data structure of FIFO 19 at this time is shown in FIG. In the figure, EAl, EA2, . ......,EA
Addresses are set in the order of i, ...EAm,
This shows how the addresses are output in order. Let us describe how to utilize the FIF (519) set as shown in FIG.

First, data import begins. FIFOl9
The address EAL of is read out. This address EAL is the start address of channel CH1, and
1st data]・1 is stored in EAl of the main memory. At the same time, the read data is incremented by 1 via the Add-1 circuit 20 and stored as data EAl+1 at the address where EAm of FIFO 19 was set. By the way, at the stage when EA1 is read, the contents of FIFO19 are shifted one step downward in FIG.
The data m is EA. ．． It has been shifted to the location where the data /1 existed. Next, address EA2 is read and the first data of channel CH2 is stored at address EA2 of the main memory. Thereafter, the first data is sequentially stored in the main memory address specified for each channel. At the stage when this first data storage is completed, the contents of FIFO 19 are EAm+1, EAm/1+1, . . . from the upper word in FIG.
・EAi+1,..., EA2+1, EA1+1
becomes. The second data for each channel is then sequentially stored in the main memory according to the set address of this FIFO 19. The data stored in the main memory through this process becomes as shown in FIG. Figure 8 shows the FIFOl
9 shows the change process of the data. Ultimately, EA
l+N, EA2+N, EAi+N, ......, EA
! 11+n, and data storage is performed according to this address. According to the above embodiment, the time series data of each input channel is programmed for each channel in the main memory and stored in the order of the time series data.
Data editing operations, which are essential in the conventional technology, are no longer necessary in the present invention, which has a great effect on improving processing performance, especially for vibration table control, vibration measurement, cycling, digital telemeter input/output control, etc. The effect is remarkable when applied to systems with large input/output time constraints.

In the above embodiments, an input system for multi-channel time-series data has been described, but it is clear that the same applies to an output system.

Furthermore, as a way to update the address, add 1 to the address.
(+1) Add-1 configuration was adopted, but generally (+
Cases other than 1) may also be used. In short, it will be incremented. According to the present invention, there is no need for data editing processing, which is effective in improving data processing speed.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a conventional example, FIG. 2 A and b are time charts thereof, FIG. 3 is a specific circuit diagram of the conventional example, and FIG. 4 is a data storage configuration diagram in the main memory at that time. FIG. 5 is a diagram of an embodiment of the present invention, FIG. 6 is a data configuration diagram of a FIFO which is an embodiment of the present invention, FIG. 7 is a data storage diagram of the main memory at that time, and FIG. 8 is a diagram of a FIFO FIG. 2 is a diagram showing the flow of data. 13...Data counter, 9...Fast-in-fast-out register.

Claims (1)

[Claims] 1. In a direct memory accelerator control device that is interposed between an input/output device and the main memory and allows data communication to be performed directly between the input/output device and the main memory without using the central processing unit, the main memory A fast-in-fast-out register is provided as a register in which an access address is set, and the main memory is accessed according to the address set in the register, and the address read from the register is incremented and the register is read again. A direct memory access control device that stores data in the memory and sequentially performs subsequent accesses.