JPH0644258B2 - DMA transfer destination buffer setting method - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a DMA (Direct Memory Access) transfer system, and more specifically, to information for designating a buffer on a main storage device constituting the DMA transfer system. ,
The present invention relates to a DMA transfer destination buffer setting method for prompt setting in a DMA control device.

[Background of the Invention]

In a system such as a communication control device or a bucket exchange that performs a DMA transfer, when a DMA transfer activation request is generated, the DMA control device issues a DMA transfer activation request to the main control device that manages the main storage device, and the main control device , From multiple buffers on the main memory under the control of its own device,
One empty buffer is selected, and the DMA controller is notified of information for designating the selected empty buffer. Then, the DMA control device determines the buffer based on the information notified from the main control device.

However, when data transmitted at high speed through a communication line or the like is received by a data receiving device and is transferred to a buffer on the main storage device by DMA transfer, the reception of the data is detected. Since there is a short time margin from issuing the DMA transfer activation request signal to DMA-transferring the received data, there is a problem that the data processing is not appropriate and the conventional empty buffer setting cannot be applied as it is. The reason for this is that a lot of time is required from when a DMA transfer request is issued to when the DMA transfer is actually started.

[Object of the Invention]

It is an object of the present invention to provide a DMA transfer destination buffer setting method capable of solving the above-mentioned drawbacks of the prior art and shortening the time from the generation of a DMA transfer activation request signal to the start of DMA transfer.

[Outline of Invention]

For the above purpose, the present invention is such that the main control device that manages each reception buffer on the main storage device can update the write address indicated by the write address pointer provided in the queue management device, While the empty reception buffer designating information is written to the reception buffer designating queue according to the write address, the queue management is performed by the DMA control device that is activated based on the DMA transfer activation request from the data receiving device when the external data reception is started. The read address pointer provided in the device is directly accessible, and while the read address indicated by the read address pointer is updatable, the empty receive buffer designation information is DMAed from the receive buffer designation queue according to the read address. After being read by transfer,
In the empty reception buffer indicated by the empty reception buffer designation information, the data from the data reception device is DMA-transferred and stored under the control of the DMA control device.

Example of Invention

An embodiment of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 shows the configuration of a DMA transfer system to which the present invention is applied. In the figure, 1 is a CC bus, 2 is a main control unit, 3 is a main storage unit, 4 is a queue management unit, and 5 is a DMA control unit. , 6 are data receiving devices. Further, 31 is a buffer group consisting of n buffers for accumulating data sent by DMA transfer provided in the main memory device 3, and 32 is a start address of each empty buffer in a specific area on the main memory device 3. A buffer designation queue for storing as a FIFO. 41 is a write address pointer that specifies the position to write when writing the start address of the empty buffer to the buffer specification queue 32, and 42 is read that specifies the position to read when reading the start address of the empty buffer from the buffer specification queue 32 The address pointer 43 is a queue management circuit that monitors the contents of the write address pointer 41 and the read address pointer 42 and detects an underrun of the buffer designation queue 32.

When the buffer 31-i of the main storage device 3 becomes free, the main controller 2 reads the write address of the buffer designation queue 32 from the write address pointer 41 of the queue management device 4, and according to the write address, the buffer designation queue 32.
Ai, which is the start address of the empty buffer, is written in, then the write address is updated, and it is written in the write address pointer. On the other hand, the data receiving device 6
When a specific pattern indicating the start of data is detected on the communication line, a DMA transfer start request signal is issued to the DMA controller 5. Upon receiving the DMA transfer activation request signal, the DMA control device 5 reads the read address of the buffer designation queue 32 from the read address pointer 42 in order to determine an arbitrary buffer from the DMA transfer destination buffer group 31. In accordance with the read address, the head address (for example, Aj) of the buffer is directly read from the buffer designation queue 32 by using DMA transfer and set in the own device. This means that the buffer 31-j has been allocated for this DMA transfer. Then, the read address is updated and written in the read address pointer.

Thereafter, the DMA control device 5 controls the DMA transfer between the data receiving device 6 and the buffer 31-j every time the DMA transfer request is received from the data receiving device 6 according to a known control method. Then, the data receiving device 6 detects the specific pattern indicating the end of the data, and sends D to the DMA control device 5.
When the MA transfer end request is issued, the DMA controller 5 reports the end of the DMA transfer to the main controller 2.

Next, the queue management device 4 of FIG. 1 will be described in more detail. FIG. 2 shows a block diagram of the hardware that realizes the queue management device.

As shown in FIG. 2, a write address pointer 41 is configured by a flip-flop (representing a plurality of flip-flops, the same applies to the following flip-flop 420) 410 and gate circuits 441 and 443.
The read address pointer 42 is composed of 444, 445, the OR gate 450 and the delay element 460, and the queue management circuit 43 for detecting an underrun is composed of the comparator 430.

Further, 101, 102 and 103 are a signal line for reading a write address pointer, a signal line for writing a write address pointer and a signal line for writing a read address pointer from the main controller 2, respectively. 501 and 502 are a signal line for reading a read address pointer and a signal line for writing a read address pointer from the DMA control device 5, respectively. The signal lines 101 to 104 are C shown in FIG.
The main controller 2 is connected via the C bus 1 and the signal lines 501 to 504 are connected to the DMA controller 5 via the signal line group 51 shown in FIG.

When the main controller 2 reads the write address pointer and executes the instruction, the signal line 101 becomes active, the gate 443 is opened, and the content of the flip-flop 410 is changed to the CC bus 1
And is taken into the main controller 2. On the contrary, when the main controller 2 executes the write address pointer write command, the content to be written is output to the CC bus 1. Its contents reach the D input of flip-flop 410 via gate 441 and are set in flip-flop 410 by signal line 102 activated by the instruction. Also in the flip-flop 420, the same operation as that of the flip-flop 410 described above is performed by the instruction of the DMA control device 5. However, when setting the flip-flop 420, the circuit of FIG. 2 defines that the instruction execution of the DMA controller 5 and the instruction execution of the main controller 2 compete with each other. If you run
There is no problem because the DMA control device 5 is controlled externally so as not to issue an instruction.

In the queue management device 4, the overrun in which the write address pointer overtakes the read address pointer is caused by the buffer designation queue 32 with respect to the number n of the buffers 31.
The problem can be solved by increasing the capacity of. Therefore, it suffices to detect only the underrun in which the read address pointer overtakes the write address pointer. Therefore, in this embodiment, as the queue management circuit 43, a comparator 430 is provided which detects that the contents of the write address pointer and the read address pointer match. Then, when the contents match, an underrun occurs, and the signal line 504 is activated to the DMA controller 5 to notify it. When the DMA control device 5 receives the DMA transfer activation request from the data receiving circuit 6 while the underrun is occurring, the DMA control device 5 reports to the main control device 2 that the activation request was not accepted due to the underrun.

According to this embodiment, the queue management device 4 can be used to manage the buffer designation queue 32 set in the main storage device 3. Moreover, the queue management device has a small amount of hardware and a simple circuit configuration. It will be easy. Also,
Since the time from the DMA transfer start request to the start of the DMA transfer can be shortened, the high-speed data from the communication line is received, and the received data is transferred by the DMA transfer to the main storage device. After detecting the reception of
Even in a device in which it takes a short time to start data transfer, the DMA transfer destination buffer is dynamically set and DM
A transfer can be performed.

〔The invention's effect〕

According to the present invention, as is clear from the above-mentioned embodiment, D
There is an advantage that the time from the MA transfer activation request to the start of the DMA transfer can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing a concrete configuration of the queue management device shown in FIG. 1, and FIG. 1 is a configuration diagram of a DMA transfer system according to the present invention. It is a figure. 1 ... CC bus, 2 ... Main control device, 3 ... Main storage device, 4 ... Queue management device, 5 ... DMA control device, 6 ... Data receiving device, 41 ... Read address pointer, 42 ... ... write address pointer, 43 ... queue management circuit, 51 ... signal line group, 410, 420 ... flip-flop, 430 ... comparator, 441 ... gate, 442 to 445 ... tri-state output gate, 450 ... or gate , 460 …… Delay element.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tetsuo Takemura 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi Ltd. Totsuka factory (72) Inventor Shinobu Gohara 216 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Ceremony Company Hitachi Totsuka Plant (72) Inventor Tatsuro Takahashi 3-9-11 Midoricho, Musashino-shi, Tokyo Inside Nippon Telegraph and Telephone Public Corporation Musashino Telecommunications Research Institute (72) Naoya Niigaki 3--9 Midoricho, Musashino City, Tokyo No. 11 inside the Musashino Telecommunications Research Institute, Nippon Telegraph and Telephone Public Corporation (72) Inventor Yasumasa Iwase 3-9-11 Midoricho, Musashino City, Tokyo Inside the Musashino Telecommunications Research Institute, Nippon Telegraph and Telephone Public Corporation (56) Reference JP-A-55-30707 ( JP, A) JP-A-57-203124 (JP, A)

Claims (1)

[Claims] 1. An external data received by a data receiving device, in which a main storage device, a DMA control device, a data receiving device and a queue managing device are accommodated in a main controlling device as an overall system controlling device via a common bus. Under the control of the DMA controller based on the free reception buffer designation information from the reception buffer designation queue on the main storage device, one of the reception buffers set in the main storage device via the common bus becomes empty. Selective DM in a certain receive buffer
A DMA transfer destination buffer setting method in a DMA transfer system designed to be transferred and stored, in which a write is provided in the queue management device by a main control device that manages each reception buffer on the main storage device. While the write address indicated by the address pointer is updatable, the empty reception buffer designation information is written to the reception buffer designation queue according to the write address, and at the same time the DMA transfer is activated in response to the start of external data reception from the data receiving device. The read address pointer provided in the queue management device is directly accessible by the DMA controller that is activated based on the request, and the read address indicated by the read address pointer is updatable while the read address pointer is updatable. According to the receive buffer specified queue from the empty receive buffer After the constant information is read out by the DMA transfer, the data from the data receiving device is DMA-transferred and stored in the empty receiving buffer indicated by the empty receiving buffer designating information under the control of the DMA controller. DMA transfer destination buffer setting method.