JPS5953634B2 - computer system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a computing system that can operate not only as a virtual computer using a multiple virtual memory system, but also as a normal computer system using a multiple virtual memory system.

In a computer system using multiple virtual memory, there is a space identifier (hereinafter referred to as space 1D), and a match in space 1D is TL.
This is one of the conditions for BFOUND, but in the case of a common space (segment), space D is ignored.

In a conventional virtual machine system using multiple virtual memory, entries in a translation lookaside buffer (hereinafter referred to as TLB) include logical addresses, system absolute addresses, virtual machine identifiers (hereinafter referred to as VM-D), and space identifiers (hereinafter referred to as VM-D). ,
Space ID) and common segment bits indicating that it is a common space are registered, and the NTL
When searching for B, the common segment bit is
1", the spaces 1D are forced to match. When operating a computer system that can also operate as a virtual computer system using multiple virtual memory as a normal computer system using multiple virtual memory, VM
- Since the 1D field is no longer needed, the unused VM-D
Attempts have been made to expand space D using fields.

When the number of bits in the space 1D increases, a large number of virtual spaces can be identified, and as a result, the number of TLB purges can be reduced. In a virtual computer system with multiple virtual memory system, the logical address, system absolute address, VM-1D, and space 1D are written to the TLB, and in a normal computer system with four multiple virtual memory systems, the logical address, system absolute address, and extended space 1D are written in the TLB.
When configuring a computer system to write 1D to the TLB, the problem is how to display the common space, and how to force the space 1D to match when it is a common space. .

The present invention solves the above problem, and can operate not only as a virtual computer system using multiple virtual memory, but also as a normal computer system using multiple virtual memory, and moreover, when the normal computer system is used, the space is 1D.
In a computer system configured to extend
The purpose is to provide a computer system that can easily and rationally solve common space problems.

Therefore, the computer system of the present invention is a computer system that can operate not only as a virtual computer system using a multiple virtual memory method, but also as a normal computer system using a multiple virtual memory method, and is capable of operating as an ordinary computer system using a multiple virtual memory method, and is capable of operating as a normal computer system using a multiple virtual memory method, and is capable of operating as a normal computer system using a multiple virtual memory method.・It has a register, a control register in which the segment table start address is set, an extended control register in which a virtual machine number that uniquely indicates a virtual machine is set, and multiple entries, and each entry has multiple common・Common segment field that stores segment bits; when operating as a virtual computer system with multiple virtual memory method, an m-bit virtual space identifier is stored; when operating as a normal computer system with multiple virtual memory method, it stores an m-bit virtual space identifier. Bit O (first bit) to vtm- of the extended virtual space identifier
The first identifier field has an m-bit configuration in which data of 1 is stored, and when operating as a virtual computer with a multiple virtual memory system, an n-bit virtual machine identifier is stored. bit m or bit m of the extended virtual space identifier when operating as
an address translation index buffer having a second identifier field in which +n-1 data is stored, a logical address field in which a portion of a logical address is stored, and a system absolute address field in which a system absolute address is stored; and a computer system. When operating as a virtual computer system using multiple virtual memory, it generates an m-bit virtual space identifier based on the contents of the control register, and also generates an n-bit virtual machine identifier based on the contents of the extended control register. If the computer system is operating as a normal computer system with multiple virtual memory, m+n is generated based on the contents of the control register above.
An identifier generation circuit that generates an extended virtual space identifier with a bit configuration; and an extended virtual space with an m+n bit configuration, which is a combination of an m-bit virtual space identifier generated by the identifier generation circuit and an n-bit virtual computer identifier. an output register in which an identifier is set; a read register in which the contents of the entry read from the address translation index buffer are set; the contents of the first identifier field of the read register and bits O to B of the output register; a first comparator that compares the data of bit m-1 with the data of bit m-1 of the output register, and a second comparator that compares the contents of the second identifier field of the read register with the data of bit m to bit m+n-1 of the output register. and a third comparator for comparing the contents of the logical address field of the read register with a portion of the address set in the address register;
If the bit has a predetermined logic value, a match is output regardless of the comparison result of the first comparator, and if the predetermined common segment bit has another logic value, a match is output. is a first forced matching means that outputs the comparison result of the first comparator as it is, and when another predetermined common segment bit of the read register has a predetermined logical value, A match is output regardless of the comparison result of the second comparator, and if the other predetermined common segment bits have other logical values, the comparison result of the second comparator is output as is. a second forced matching means, the first forced matching means, the second forced matching means, and the third forced matching means;
and means for outputting a signal indicating that a system absolute address corresponding to the logical address exists in the address translation index buffer when all of the comparators output matches. . Hereinafter, the present invention will be explained with reference to the drawings. FIG. 1 is a diagram explaining the allocation of main memory in a virtual computer system, FIG. 2 is a diagram illustrating an example of an address translation mechanism according to the present invention, FIG. 3 is a block diagram of an example of an identifier generation circuit, and FIG. The figure is a diagram illustrating forced matching in space 1D using common segment bits.

As shown in Figure 1, virtual machines VM#1, VM#2,
...VM#1 region for each VM#l,
VM#2 region, . . . VM#i region are given.

VMMIJ is assigned to a virtual machine monitor. The VMM region is divided into a VMM prefix area and a MM program area. VM#
The i region is also divided into a VM#i prefix area and a VM#l program area.

A system absolute address is an address used by the program that manages the host machine (VMM program), and is used to access all areas of the host machine's main memory (including the VM program area and VM prefix area). It is possible. What is region absolute address?
Starts the region given to the virtual machine.
The address is set to 1011, and addresses are assigned continuously in the direction of increase in the system absolute address, and the end address is the region absolute address for the maximum allocated system absolute address, and the VM program is It is also the lowest level of address that can be recognized. The start address of the VM#1 region assigned to the virtual machine VM#i is set in the region base address register RBA, and its final address is set in the region limit register RBA.
Set in address register RCA. In Figure 2, 1 is the TLB, 2 is the address register, 3-
1 to 3-3 are comparators, 4-1 and 4-2 are 0R circuits,
5 is a common segment bit creation circuit, 6 is an AND
circuit, 7 is an address conversion processing unit using a DAT table;
8 is a prefix processing unit, 9 is an adder, 10 is a region base address register, 11 is a read register, 12 is a control register, 13 is an extension control register, 14
15 indicates an identifier generation circuit, and 15 indicates an output register. Also, AU is the upper part of the logical address, AM is the middle part, AL is the lower part, SAU is the system absolute address, ID-0 and ID-1 are the identifiers, and 0S0 and 0S1 are the common segment bits, respectively. . The address part AL is an intra-page address, and the system absolute address is for a page. When the computer system operates as a virtual machine system using multiple virtual memory, VM-D for identifying the virtual machine is written in the D-1 field of TLBl, and VM-D for identifying the virtual machine is written in the D-0 field. Space 1D for identifying the space is entered.

Control register 12 is a segment table starting point address register. The extended control register 13 stores a virtual machine number that uniquely designates a virtual machine. The identifier generation circuit 14 has a configuration as shown in FIG. In FIG. 3, 16 is an STO stack, 17 is a hashing circuit, 18 and 19 are comparison circuits, and 20 is an AND circuit. When operating as a virtual computer system with multiple virtual memory method, D-0 is space 1.
D, and ID-1 becomes VM-1D. However, M-1D is generated by hashing the contents of the extended control register 13, and the space ID is generated by hashing the contents of the control register 12. The hash circuit 17 performs the eight-hash processing described above.
The output of is set in the output register 15. The output of hashing circuit 17 also indicates the entry address of STO stack 16. The contents of the control register 12 and the contents of the extended control register 13 are written to the entry of the STO stack 16. When the contents of the control register 12 and extended control register 13 are changed, the contents of the STO stack 16 are read, and if there is no match with the contents of the control register 12 and extended control register 13, a TLB purge command is issued. Send to TLBl. The address conversion processing unit 7 based on the DAT table
When LB is NOTFOUND, a logical address is converted into a real address using a segment table, a page table, etc., and the prefix processing unit 8
processes real addresses to generate regional absolute addresses. The adder 9 adds the contents of the RBA register 10 to the relative absolute address to generate a system absolute address. When operating as a virtual computer system, the common segment bit creation circuit 5 generates a logic "if a flag indicating a common area is added to the segment table used by the address translation processing unit 7. Common Segment Bit CSO of “1” and Common Segment Bit C of Logic “0”
Output Sl. Also, if the segment table does not have a flag indicating that it is a common area,
Common segment bit CSO with logic “O” regardless of whether it is a virtual computer system or a normal computer system.
and a common segment bit CSl of logic [0]. When the common segment bit creation circuit 5 operates as a normal computer system, if a common area is displayed in the segment table used by the address conversion processing unit 7, the common segment bit generation circuit 5 generates a common segment bit of logic "1". Outputs segment bit CSO and common segment bit CS1 of logic "1". When the computer system operates as a normal computer system, the ID-0 field and ID-1 field of TLB1 are assigned to space 1D. Now, assuming that the D-0 field has an m-bit configuration and the D-1 field has an n-bit configuration, in a normal computer system, the hashing algorithm of the hashing circuit 17 in FIG. 3 is changed,
Based on the contents of the control register 12, an m+n bit space 1D that can take 2m+n patterns is generated. T.L.
When searching Bl, the contents of the entry corresponding to address portion AM are read to read register 11.

When common segment bits C$0 and CS1 are both logic [0], a match of ID-0 and a match of ID-1 are the TLBFUND conditions. Common segment bit CSO is logic ``1'' and CSl is logic [
0], D-0 is forced to match, and D-
A match of 1 becomes the TLBFUND condition. When common segment bits CSO and CS1 are both logic [1], ID-0 and ID-1 are forced to match. FIG. 4 explains forced matching of identifiers using common segment bits CSO and CS1.

As can be seen from FIG. 4, in the virtual machine system, space 1D and VM-1D are written to the entry of TLB1, and space 1D sets the common segment bit CSO to logic "1".
”, it is forced to match. In a normal computer system, expanded space 1D is written in the M-1D field of TLB1. The space D in a normal computer system consists of common segment bits CSO and CSL.
A match is forced by setting both to logic "1". When operating as a virtual machine system, when the control register 12 and extended control register 13 are changed, the segment read from the STO stack 16
The table start address and the segment table start address of the control register 12 are compared, and the read virtual machine number and the virtual machine number of the extended control register 13 are compared.

When a mismatch in segment table start addresses or a mismatch in virtual machine numbers is detected, a TLB purge command and spaces 1D and M-1D are sent to TLB1. When TLB1 receives a TLB purge command, it purges entries with the same spaces 1D and VM-D, but if only the segment table start address does not match, the common segment bit CSO is set to logic "1".
Exclude entries from being purged. As is clear from the above description, according to the present invention, the common space problem can be easily solved in a computer configured to expand the space D using M-1D, which is unused in a normal computer system. And it can be solved rationally.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the allocation of main memory in a virtual computer system, FIG. 2 is a diagram illustrating an example of an address translation mechanism according to the present invention, FIG. 3 is a block diagram of an example of an identifier generation circuit, and FIG. The figure is a diagram illustrating forced matching in space 1D using common segment bits. 1...TLB, 2...Address register, 3-1 to 3-3...Comparator, 4-1
and 4-2...0R circuit, 5...common segment bit creation circuit, 6...AND
Circuit, 7... Address exchange processing unit based on DAT table, 8... Prefix processing unit, 9...
... Adder, 10 ... Region base ● Address ● Register, 11 ... Read register, 12 ... Control register, 13 ... Extension Control register, 14...Identifier generation circuit, 1
5... Output register.

Claims (1)

[Claims] 1 A computer system that can operate not only as a virtual computer system using a multiple virtual memory method, but also as a normal computer system using a multiple virtual memory method, which has an address register in which a logical address is set, and a segment table starting address. a control register in which is set a virtual machine number, an extended control register in which a virtual machine number uniquely indicating a virtual machine is set, and a common register having multiple entries and each entry storing multiple common segment bits. When operating as a virtual computer system using the segment field multiple virtual memory method, an m-bit virtual space identifier is stored; when operating as a normal computer system using multiple virtual storage method, bits 0 to bit m of the extended virtual space identifier are stored. -1 data is stored in the m-bit first identifier field, and when operating as a virtual machine with multiple virtual memory system, an n-bit virtual machine identifier is stored and operates as a normal computer with multiple virtual memory system. bit m or bit m+n-1 of the extended virtual space identifier
an address translation index buffer having a second identifier field in which data is stored, a logical address field in which a portion of a logical address is stored, and a system absolute address field in which a system absolute address is stored; When operating as a storage-based virtual machine system, an m-bit virtual space identifier is generated based on the contents of the control register, and an n-bit virtual machine identifier is generated based on the contents of the extended control register. When the computer system operates as a normal computer system with multiple virtual memory, an identifier generation circuit that generates an m+n bit extended virtual space identifier based on the contents of the control register, and m generated by the identifier generation circuit. An output register in which a combination of a bit-configured virtual space identifier and an n-bit-configured virtual machine identifier or an m+n-bit extended virtual space identifier is set, and the contents of the entry read from the address translation index buffer mechanism. a read register to be set; a first comparator that compares the contents of a first identifier field of the read register with data from bit 0 to bit m-1 of the output register; a second comparator for comparing the contents of the identifier field with the data of bit m to bit m+n-1 of the output register; and the contents of the logical address field of the read register and the address set in the address register. and a third comparator that compares a portion of a first forced matching means that outputs a match and outputs the comparison result of the first comparator as is when the predetermined common segment bit has another logical value; If the other predetermined common segment bits have a predetermined logical value, a match is output regardless of the comparison result of the second comparator, and the other predetermined common segment bits a second forced matching means that outputs the comparison result of the second comparator as it is when the logical value of A computer system comprising means for outputting a signal indicating that a system absolute address corresponding to a logical address exists in an address conversion index buffer when all comparators output matches.