JPS5925303B2 - Multiple virtual memory control method in multiple virtual computer system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multiple virtual computer system that employs a multiple virtual space processing method, and in particular, to a system that performs correspondence between logical addresses and real addresses in response to multiple virtual spaces, and also provides a method for making correspondence between logical addresses and real addresses. In a data processing system in which the results of the processing are stored in a comparison table, a common area specifying storage means for specifying a common area common to each virtual space is provided,
When storing the correspondence results between logical addresses and real addresses corresponding to the common area on the above comparison table, they are commonly registered regardless of the difference in virtual space, thereby improving the utilization efficiency of the comparison table. This relates to a multiple virtual space processing data processing system A.

In recent data processing systems, it has become common to employ a so-called virtual storage method. There is also a trend in virtual memory systems, from a single virtual memory system consisting of only one address space to a multiple virtual memory system consisting of a plurality of address spaces. In the multiple virtual storage system, only one job exists in one virtual space, and as many virtual spaces are prepared according to the number of jobs that operate simultaneously (job multiplicity). The method of using such virtual space is
It has the advantage that only one job is assigned to one space and is not affected by the operating status of other jobs. It also has the advantage of not being limited by the hardware architecture when it comes to increasing spatial multiplicity. In this case, an area common to each job, that is, an area for the control program, control tables used in the control program, and common subroutines, is provided for each virtual space. Such an area is called a common area. Even in the case of the multiple virtual memory method described above, the process of associating addresses in the virtual space with real addresses on the main memory is performed for each virtual space, just as in the case of a single virtual space. It will be done.

The results of this matching are stored in a high-speed storage device called a translation lookaside buffer (TLB), that is, a comparison table, and when processing is to proceed, the comparison table is indexed to determine the logical address and real address. It will be made to correspond to the above. However, as described above, within the common area prepared for each virtual space, the correspondence between logical addresses and real addresses is always constant even if the virtual spaces are different. For this reason, if it is attempted to store different correspondences in the comparison table TLB each time the virtual space differs for this area, the utilization efficiency of the comparison table TLB will decrease.

Therefore, one of the purposes of the present application is to store areas common to multiple virtual spaces in the TLB in only one entry, so that entry 1 can be commonly used for multiple virtual spaces. It is in.

Furthermore, recently, the concept of multiple virtual machines has begun to be adopted.

This is a method of running multiple operating systems (hereinafter referred to as OS) on one hardware system to proceed with processing as if a plurality of different computers virtually existed. Naturally, since each virtual machine (that is, each OS) adopts a virtual storage method, the control of the TLB is also extended to multiple systems. Another object of the present invention is to realize efficient TLB control in a multiple virtual machine system. This will be explained in detail below with reference to the drawings. 1 and 2 are explanatory diagrams conceptually explaining the structure of multiple virtual storage in a data processing system that performs processing for multiple virtual spaces.
-0 to 1-n are virtual spaces, 210 to 2-n, respectively.
are segment tables, 3-00, 3-10, .
・・・・・・ 3-10, 3-11, ・・・・・・, 3-
NO, 3-Nl,..., 4-0, 4-1,...
. . , 5-0, 5-1, . . . represent page tables, respectively.

That is, as shown in FIG. 1, a plurality of virtual spaces 1-0 to 1-n are allocated to each job. The number is primarily limited by the operating system;
Currently, it is possible to handle about 1500 multiplexed spaces. Each virtual space 1-0 to 1-n has two common areas, area A and area B, and an area C called an individual user area. Commonly prepared for 1 to 1 to n. In order to match the relationship between the address of the virtual space and the address of the real space on the main memory for each virtual space, the second
As shown in the figure, segment tables 2-0 to 2-n
and page table 3-00, 3-01,...
,3-10,3-11,...,3-NO,3-
Nl,...,4-0,4-1,...,
5-0, 5-1, . . . are prepared.

Each segment table 2-0 to 2-n corresponds to one virtual space 1-0 to 1-n, respectively. To designate or identify one virtual space among a plurality of virtual spaces, the first address of the segment table is designated. In order to specify the start address, for example, a register called a segment base register (SBR) is used. The process of determining a real address from a logical address for a certain virtual space can be considered to be performed as follows.

That is, based on the contents of the segment base register SBR corresponding to one virtual space, for example 1-1, and a partial bit of a given logical address, the segment table 2-1 shown in FIG. One address above is accessed. Then, one address on one page table, for example, 3-11, is accessed based on the contents of the address in the segment table 2-1 and the other bits of the logical address. and the page table 3
The real address is determined based on the contents of the address of -11 and the remaining bits of the logical address. The result of the correspondence between the determined logical address and real address is stored on the above-mentioned comparison table TLB. In subsequent processing, the comparison table TLB is first indexed to check the correspondence between logical addresses and real addresses to determine the real address. Of course, if the correspondence between the logical address and the real address is not stored in the comparison table TLB, the real address is determined again using the segment table 2, page tables 3, 4, 5, etc. and stores the result on the comparison table TLB. At this time, the comparison table TL
Since the storage capacity of B is limited, for example, one correspondence result that has not been used most recently at that point in time is removed from the comparison table TLB, and a new correspondence result is stored.
By the way, in the multiple virtual space system, even if the logical address is the same, if the virtual space is different, the correspondence with the real address will be different.

(Although they are the same in the common area.) Therefore, every time the space to be used changes, all the old contents of the TLB must be invalidated before storing the logical/actual correspondence for the new space. There is a risk of confusion between the two. However, although it is desired to proceed with processing by dynamically switching spaces, if all TLBs are invalidated every time a space is switched as described above, the efficiency of TLB usage will not increase. Therefore, information that identifies the space (hereinafter referred to as space 1D) is added to the information stored in the TLB,
Even if the same logical/actual correspondence as the target is stored, if the space D does not match the space D of the currently running program, it will not be used. Also, one virtual space corresponds to one segment table, and as mentioned above, there are hundreds to thousands of virtual spaces, so the space D that distinguishes them is
This means that around 10 bits are required.

However, generally simultaneously and in parallel (in fact, time-sharingly)
Since the number of virtual spaces used is several dozen at most, the following measures have been taken. That is, for several virtual spaces that will be used for the time being, an STO stack is provided for registering the start address of the corresponding segment table (referred to as segment table origin - STO) and assigning a series of ID numbers to each virtual space. , this STO-T
D is used as space 1D. Now, when performing address translation using such a TLB and STO stack, the first purpose mentioned above, that is, the TLB and STO stack related to the common area.
In order to store data in the LB only once and to be able to use it in common even if the virtual spaces are different, the following can be done. A 1-bit flag bit is provided in the TLB, and in the case of logical/real correspondence regarding the common area, it is set to, for example, ``1''.When the bit is ``1'', the flag bit of space D (STO-D) is set. As long as the logical addresses match, regardless of whether they match or do not match, it can be used. Also, in the virtual computer method, there is no particular problem as long as one virtual computer corresponds to one virtual space. Space D may be used as is as virtual computer D. However, it is natural that each virtual computer may adopt a multiple virtual space method. In this case, it is necessary to distinguish between a common area in one virtual computer and a common area in other virtual computers. This is because each virtual machine is independently controlled by a separate OS, and the size and position of the common area may also be different. Therefore, in order to deal with this, it is necessary to store the virtual machine 1D in the TLB in addition to the space 1D, or store it in the TLB for each virtual space even if it is a common area. The former has the disadvantage that the capacity of the TLB becomes large and the control becomes complicated, while the latter has the disadvantage of reducing TLB usage efficiency.

In order to solve such drawbacks, the present invention focuses on the point that STO-1D does not match in the common area,
Only in that case, instead of STO-1D, virtual computer 1D (
(hereinafter referred to as M-1D).

An embodiment of the present invention will be explained in detail below with reference to FIG. In the figure, 11 is a logical address register, and a part 112 of its contents is used to index TLB12.

A part 121 of the resulting output and a part 111 of the logical address register 11 are compared by the comparator 18, and if they match, the other part 122 of the output is the target real address. be. However, since it is a multiple virtual space system, it is also necessary to check the space 1D.

Therefore, the comparator 19 compares the output 1D124 of TLBl2 with the contents of the STO-1D register 15 indicating the space 1D in the currently running program, and if they match, the AND gate 20 performs an AND operation with the previous comparison result. As a result, the gate 21 is opened and the contents of the real address register 13 are made available. However, the ID comparison with the STO-ID register 15 is performed only when the common area designation flag bit 123 in the TLB is "O". When this flag bit 123 is "1", the multiplexer 16 VM-D register 14 is selected by TL
It is compared with IDl24 from B. Also, if there is a mismatch in either the comparator 18 or 19, the segment table and page
Find the real address using the table and send the result to TLB
Store in. The address STO of the segment table to be used at this time is obtained from the STO stack 17. That is, the STO- which matches the contents of the STO-1D register 15
1D in the STO stack 17 and thereby access the segment table in main memory. In addition, if an indication is provided in each segment table to determine whether it is a common area or not, the indication can be read when indexing the segment table and the flag bit 12 of the TLB can be read.
You can store it in 3. Furthermore, when storing to TLB12, the multiplexer 16 is simultaneously switched depending on the contents stored in the flag bit 123, and the data is stored in either VM-1D or ST.
The force of O-1D is stored together as TLB (7) IDl24. In addition, STO-1D has each segment
This is for distinguishing tables, and the correspondence is managed using the STO stack 17, and the register 15 is reset each time the space is switched.

On the other hand, VM-1D distinguishes each virtual machine (ie, 0S), and is reset to the register 14 every time the 0S is switched. Also, if you want to use a new segment table that is not registered in STO stack 17, use the old STO stack 17.
11) of the old STO, and register a new STO by expelling one of them, and registering a TLB with the same ID as 11) of the old STO.
Invalidate the entry (however, since the flag bit 123 is "1", it is VM-1, so invalidation is not necessary).As described above, in the present invention, the common area designation flag 123 is set in the TLB.
and two types of IDs, namely VM-1D and STO.
-1D is provided, and VM-1D is used when the flag 123 indicates a common area, and STO-1D is used at other times, without reducing TLB utilization efficiency or increasing TLB capacity. , it is possible to enable a multiple virtual computer system that adopts a multiple virtual space system.

[Brief explanation of the drawing]

Figures 1 and 2 are conceptual explanatory diagrams of the multiple virtual space system;
FIG. 3 is a block diagram of one embodiment of the present invention. In the figure, 11 is a logical address register, 12 is TLBll
3 is a real address register, 14 is a virtual machine 1D, 15
is STO-1D, 16 is multiplexer, 17 is STO
Stack, 18 and 19 are comparators, and 123 is a common area designation flag.

Claims (1)

[Claims] 1 Translation look aside buffer (TLB) that stores the correspondence between logical addresses and real addresses
In a data processing system having a common area designation flag bit and an identifier (ID) information bit in the TLB, when the flag bit designates a common area, a virtual machine ID is stored in the ID information bit, and the If the flag bit does not indicate a common area, the virtual storage space ID is stored in the ID information bit, and a register is provided to display the virtual computer ID and virtual storage space ID of the currently running program. In a multiple virtual machine system, address conversion is performed by comparing the ID value of either the virtual machine ID or the virtual storage space ID, depending on the value of the flag bit. Memory control method.