JPS596060B2 - Semiconductor device inspection method - Google Patents
Semiconductor device inspection methodInfo
- Publication number
- JPS596060B2 JPS596060B2 JP54019313A JP1931379A JPS596060B2 JP S596060 B2 JPS596060 B2 JP S596060B2 JP 54019313 A JP54019313 A JP 54019313A JP 1931379 A JP1931379 A JP 1931379A JP S596060 B2 JPS596060 B2 JP S596060B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- wire
- bonding
- lead
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/0711—Apparatus therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/0711—Apparatus therefor
- H10W72/07141—Means for applying energy, e.g. ovens or lasers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07521—Aligning
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07531—Techniques
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Wire Bonding (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造過程における半導体チップの
特性検査方式に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for testing the characteristics of semiconductor chips during the manufacturing process of semiconductor devices.
所定の工程を得て製造された半導体装置は、最終的に所
望の特性が得られるか否かが検査され、その検査結果に
よつて良、不良が決定されている。この種の検査工程は
従来の半導体装置製造においては、半導体チップとリー
ドフレームとの間のワイヤボンディングが完了してから
なされていた。一方半導体チップとリードフレームをワ
イヤボンディングする場合、リード上に塔載された半導
体チップ電極にまずワイヤの一端をボンディングして第
1ボンディングとし、その後リードフレーム或いはワイ
ヤを供給するキヤピラリイのいずれかを相対的に移動さ
せて、同ワイヤの他端がボンディングされるべき領域ま
で位置調整し、位置調整後にワイヤ他端を他方のリード
にボンディングして第2ボンディングとし、半導体チッ
プとリード端子間を電気的接続する方式が採られていた
。しかも半導体チップの特性検査は上記ワイヤボンディ
ングが終了してから実行されていた。即ち従来の半導体
装置製造においてはワイヤボンディング工程及び半導体
チップの特性検査工程が夫々別途に独立した工程で行わ
れるもので、工数が多くなり作業に手間を要する欠点が
あつた。本発明は、ワイヤボンデイグ工程において、第
1ボンデ・lシダに続いて第2ボンディングが実行され
る際、第2ボンディングのためにキャピラリイとリード
との間に位置調整がなされる期間を利用して半導体チッ
プの特性検査を実行することにより従来に比べてより半
導体装置製造の効率を高めるものである。A semiconductor device manufactured through a predetermined process is finally inspected to see whether desired characteristics are obtained, and whether the device is good or bad is determined based on the inspection results. In conventional semiconductor device manufacturing, this type of inspection process was performed after wire bonding between the semiconductor chip and the lead frame was completed. On the other hand, when wire bonding a semiconductor chip and a lead frame, one end of the wire is first bonded to the semiconductor chip electrode mounted on the lead to form the first bond, and then either the lead frame or the capillary supplying the wire is bonded to the semiconductor chip electrode mounted on the lead. The other end of the wire is moved to the area where it should be bonded, and after the position adjustment, the other end of the wire is bonded to the other lead to form a second bond, and the electrical connection between the semiconductor chip and the lead terminal is established. A method of connecting was adopted. Moreover, the characteristics inspection of the semiconductor chip was performed after the above-mentioned wire bonding was completed. That is, in conventional semiconductor device manufacturing, the wire bonding process and the semiconductor chip characteristic testing process are performed in separate and independent processes, which has the drawback of increasing the number of man-hours and requiring time and effort. The present invention utilizes a period in which position adjustment is performed between a capillary and a lead for the second bonding when the second bonding is performed following the first bonding process in the wire bonding process. By performing characteristic tests on semiconductor chips, the efficiency of manufacturing semiconductor devices is improved compared to the conventional method.
次に発光ダイオードのワイヤボンディング工程を挙げて
本発明を説明する。Next, the present invention will be described with reference to a wire bonding process for light emitting diodes.
図に於て1はリードフレームで、金属板が打抜き加工等
によつて形成されている。In the figure, 1 is a lead frame, which is formed from a metal plate by punching or the like.
該リードフレーム1は半導体チップ2をダイボンドさせ
るリード端子1aと、ダイボンドされた半導体チップ2
との間でワイヤ3によつて電気的接続がなされるリード
端lbとが対をなし、該リード端子対は繰返しパターン
で複数対が同一金属板に一体的に設けられている。リー
ド端子1aに半導体チップ2が導電性ペーストを介して
ダイボンドされた後、リードフレーム1はワイヤボンデ
ィング装置のリードフレーム送り機構にセットされる。
ワイヤボンディング装置のボンディング位置には、リー
ドフレーム上の半導体チップ2の映像を取り込むための
ITVカメラ4が光学系5を介して設置されている。光
学系5に設けられた光源によりボンデインク位置に搬送
されてきた半導体チツプ2が照明されてITVカメラに
取り込まれ、形成された映像信号が信号処理回路でレベ
ル判定されてチツプ上の電極位置が認識される。認識さ
れた電極位置情報はリードフレーム送り機構成いはワイ
ヤを供給するためのキャピラリイ駆動装置に与えられ、
ボンデイングのためのワイヤ先端と半導体チツプ上の電
極との位置合せがなされる。位置合せされた半導体チツ
プ2及びワイヤ3は、キヤピラリイ6を降下押圧させる
ことによつてボンデイングされ、第1ボンデイングを終
える。次に同ワイヤ3の他端をリード1b側に第2ボン
デイングするためキヤピラリイ6或いはリードフレーム
1の相対的な移動が行われるが、該相対的な移動及び移
動後の位置調整期間に同時に半導体チツプ2の特性検査
が実行される。即ち上記第1ボンデイングによつて半導
体チツプ2には電圧印加のためのワイヤ3が既に接続さ
れているため、該ワイヤ3を介してリードフレーム1と
の間に電圧が印加され、半導体チツプを動作状態にして
発光出力、順方向電圧及び逆耐圧等の諸特性が検査され
、半導体チツプ2の電気的特性と共に第1ボンデイング
の良否が判定される。特に発光出力の検査においては半
導体チツプの電極認識に用いられるITVカメラ4が兼
用して用いられる。電圧印加によつて発光した半導体チ
ツプ出力はITVカメラ4に取り入れられ、光電変換さ
れて光出力に対応したレベルの電気信号に変換される。
該電気信号A/D変換された後、サンプリングパルスで
定期的にサンプリングされて発光面を格子状に分割し、
発光面内の各点での発光出力情報を形成する。該発光出
力情報は予め設定されたスライスレベル或いは上記第1
ボンデイング時に半導体チツプ面から形成されたデータ
で処理して背景から区別され、該処理後の発光出力情報
について各分割された領域から得られる情報を加算処理
することによつて発光出力の総和を検出することができ
る。上記発光出力の加算値は予め輝度との相関関係を求
めておくことにより、光出力を輝度に変換させることが
できる。上記半導体チツプの検査結果は半導体チップ番
号に対応してメモリに収納され、チツプ良否の判定情報
として利用される。上記実施例はワイャボンデイングの
ための撮像装置を、チツプ発光出力の検出に兼用させる
実施例を挙げたが、撮像装置及びキヤピラリイの設置さ
れる位置関係等により兼用が適切でない場合にはチツプ
出力検出のため第2の撮像装置をボンデイング位置近傍
に別途に設置して実施することもできる。The lead frame 1 includes a lead terminal 1a to which a semiconductor chip 2 is die-bonded, and a die-bonded semiconductor chip 2.
A pair of lead terminals lb are electrically connected to each other by a wire 3, and a plurality of pairs of lead terminals are integrally provided on the same metal plate in a repeating pattern. After the semiconductor chip 2 is die-bonded to the lead terminal 1a via a conductive paste, the lead frame 1 is set in a lead frame feeding mechanism of a wire bonding device.
At the bonding position of the wire bonding apparatus, an ITV camera 4 is installed via an optical system 5 to capture an image of the semiconductor chip 2 on the lead frame. The semiconductor chip 2 transported to the bonding position is illuminated by a light source provided in the optical system 5 and captured by an ITV camera, and the level of the formed video signal is determined by a signal processing circuit to recognize the electrode position on the chip. be done. The recognized electrode position information is provided to a lead frame feeder arrangement or capillary drive device for feeding the wire;
The tip of the wire for bonding is aligned with the electrode on the semiconductor chip. The aligned semiconductor chip 2 and wire 3 are bonded by pressing down the capillary 6, completing the first bonding. Next, the capillary 6 or the lead frame 1 is moved relative to each other in order to bond the other end of the wire 3 to the lead 1b side for a second time, but the semiconductor chip is simultaneously moved during the relative movement and the position adjustment period after the movement. 2 characteristic tests are performed. That is, since the wire 3 for voltage application has already been connected to the semiconductor chip 2 through the first bonding, a voltage is applied between the semiconductor chip 2 and the lead frame 1 via the wire 3, thereby operating the semiconductor chip. Various characteristics such as light emitting output, forward voltage, and reverse breakdown voltage are inspected, and the quality of the first bonding is determined as well as the electrical characteristics of the semiconductor chip 2. Particularly in the inspection of the light emitting output, the ITV camera 4 used for recognizing the electrodes of semiconductor chips is also used. The output of the semiconductor chip that emits light upon application of a voltage is taken into the ITV camera 4 and photoelectrically converted into an electrical signal at a level corresponding to the optical output.
After the electrical signal is A/D converted, it is periodically sampled with a sampling pulse to divide the light emitting surface into a grid pattern,
Light emission output information at each point within the light emitting surface is formed. The light emission output information is based on a preset slice level or the first
The data formed from the semiconductor chip surface during bonding is processed to distinguish it from the background, and the sum of the light emitting output is detected by adding the information obtained from each divided area regarding the light emitting output information after the processing. can do. The light output can be converted into brightness by calculating the correlation between the sum of the light emitting outputs and the brightness in advance. The test results of the semiconductor chip are stored in a memory in correspondence with the semiconductor chip number, and are used as information for determining whether the chip is good or bad. In the above embodiment, the image pickup device for wire bonding is also used to detect the chip light emission output. However, if the combination is not appropriate due to the positional relationship of the image pickup device and the capillary, etc., the chip output may be used. It is also possible to separately install a second imaging device near the bonding position for detection.
上記半導体チツプ2の特性検査がなされている期間に、
他方のリード端子1bにキャピラリイ6の先端を対向さ
せる位置合せがなされ、特性検査終了後に新しく位置決
めされたキヤピラリイ6は下降押圧されてワイヤ3の他
端はリード端子1bに第2ボンデイングされる。During the period when the characteristics of the semiconductor chip 2 are being tested,
The tip of the capillary 6 is aligned to face the other lead terminal 1b, and after the characteristic test is completed, the newly positioned capillary 6 is pressed down and the other end of the wire 3 is second bonded to the lead terminal 1b.
第1及び第2ボンデイングされたリードンレーム1は送
り機構によつて1ピツチ分搬送され、次のリード対にダ
イボンドされた半導体チツプがボンデイング位置にセツ
トされ、上記動作が繰返される。上記実施例は半導体チ
ツプとして発光ダイオードをワイヤボンデイングする工
程を挙げて説明したが、他の半導体チツプでも同様に本
発明を実施することができる。The first and second bonded lead frames 1 are transported by one pitch by the feeding mechanism, and the semiconductor chip die-bonded to the next lead pair is set at the bonding position, and the above operation is repeated. Although the above embodiment has been described using a process of wire bonding a light emitting diode as a semiconductor chip, the present invention can be similarly practiced with other semiconductor chips.
以上本発明によれば第1ボンデイングの状態でワイヤを
介して半導体チツプに電流を供給し、前記半導体チツプ
を試験動作せしめて前記半導体チツプの特性検査を行な
い、該特性検査後に第2ボンデイングを施こすようにし
たので、従来の如く半導体チツプの特性検査を実行する
ための別途の工程においてリードフレームをその都度セ
ツトし直すことがなく、単一のワイヤボンデイング工程
内で半導体チツプの特性検査をも完了することができる
ので、手間が著しく省けると共に、ワイヤホンデイング
時に使われる撮像装置や他の周辺機器を半導体チツプの
特性検査に兼用することができるものである。As described above, according to the present invention, a current is supplied to the semiconductor chip through the wire in the first bonding state, the semiconductor chip is put into test operation, the characteristics of the semiconductor chip are inspected, and the second bonding is performed after the characteristic inspection. This eliminates the need to re-set the lead frame each time in a separate process for testing the characteristics of semiconductor chips as in the past, making it possible to test the characteristics of semiconductor chips within a single wire bonding process. Since the process can be completed, it is possible to significantly save time and effort, and the imaging device and other peripheral equipment used during wire bonding can also be used for testing the characteristics of semiconductor chips.
又半導体装置の製造工程の数を減少させて効率化を図る
ことができるものである。Furthermore, efficiency can be improved by reducing the number of manufacturing steps for semiconductor devices.
図は本発明を説明するための要部概略図である。
1:リードフレーム、2:半導体チツプ、3:ワイヤ、
4:ITVカメラ、6:キヤピラリイ。The figure is a schematic diagram of main parts for explaining the present invention. 1: lead frame, 2: semiconductor chip, 3: wire,
4: ITV camera, 6: Capillary.
Claims (1)
を第1ボンディングし、次にワイヤの他端を他のリード
に第2ボンディングして形成される半導体装置を検査す
る為の方式であつて、前記第1ボンディングの状態でワ
イヤを介して半導体チップに電流を供給し、前記半導体
チップを試験動作せしめて前記半導体チップの特性検査
を行ない、該特性検査後に前記第2ボンディングを施す
ことを特徴とする半導体装置の検査方式。1. A method for inspecting a semiconductor device formed by first bonding one end of a wire to a semiconductor chip mounted on a lead, and then second bonding the other end of the wire to another lead. In the first bonding state, a current is supplied to the semiconductor chip through a wire to cause the semiconductor chip to perform a test operation to test the characteristics of the semiconductor chip, and after the characteristics test, the second bonding is performed. An inspection method for semiconductor devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54019313A JPS596060B2 (en) | 1979-02-20 | 1979-02-20 | Semiconductor device inspection method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP54019313A JPS596060B2 (en) | 1979-02-20 | 1979-02-20 | Semiconductor device inspection method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55111143A JPS55111143A (en) | 1980-08-27 |
| JPS596060B2 true JPS596060B2 (en) | 1984-02-08 |
Family
ID=11995915
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP54019313A Expired JPS596060B2 (en) | 1979-02-20 | 1979-02-20 | Semiconductor device inspection method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS596060B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57134944A (en) * | 1981-02-16 | 1982-08-20 | Toshiba Corp | Wire bonding device |
| JP4530984B2 (en) | 2005-12-28 | 2010-08-25 | 株式会社新川 | Wire bonding apparatus, bonding control program, and bonding method |
-
1979
- 1979-02-20 JP JP54019313A patent/JPS596060B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55111143A (en) | 1980-08-27 |
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